[SubZero] Fix code generation issues occurred in Cross-test and PNaCL smoke-tests

tests_lit/llvm2ice_tests/fp.call_ret.ll

 ; This tries to be a comprehensive test of f32 and f64 call/return ops.
 ; The CHECK lines are only checking for basic instruction patterns
 ; that should be present regardless of the optimization level, so
 ; there are no special OPTM1 match lines.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 41 matching lines @@
   ret i32 %add3
 }
 ; CHECK-LABEL: passFpArgs
 ; CHECK: mov DWORD PTR [esp+0x4],0x7b
 ; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
 ; CHECK: mov DWORD PTR [esp+0x4],0x7b
 ; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
 ; CHECK: mov DWORD PTR [esp+0x4],0x7b
 ; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
 ; MIPS32-LABEL: passFpArgs
-; MIPS32:       mfc1    a2,$f15
-; MIPS32:       mfc1    a3,$f14
+; MIPS32:       mfc1    a2,$f{{[0-9]+}}
+; MIPS32:       mfc1    a3,$f{{[0-9]+}}
 ; MIPS32:       li      a1,123
 ; MIPS32:       jal     {{.*}}  ignoreFpArgsNoInline
-; MIPS32:       mfc1    a2,$f23
-; MIPS32:       mfc1    a3,$f22
+; MIPS32:       mfc1    a2,$f{{[0-9]+}}
+; MIPS32:       mfc1    a3,$f{{[0-9]+}}
 ; MIPS32:       li      a1,123
 ; MIPS32:       jal     {{.*}}  ignoreFpArgsNoInline
-; MIPS32:       mfc1    a2,$f25
-; MIPS32:       mfc1    a3,$f24
+; MIPS32:       mfc1    a2,$f{{[0-9]+}}
+; MIPS32:       mfc1    a3,$f{{[0-9]+}}
 ; MIPS32:       li      a1,123
 ; MIPS32:       jal     {{.*}}  ignoreFpArgsNoInline
 
 declare i32 @ignoreFpArgsNoInline(float %x, i32 %y, double %z)
 
 define internal i32 @passFpConstArg(float %a, double %b) {
 entry:
   %call = call i32 @ignoreFpArgsNoInline(float %a, i32 123, double 2.340000e+00)
   ret i32 %call
 }
 ; CHECK-LABEL: passFpConstArg
 ; CHECK: mov DWORD PTR [esp+0x4],0x7b
 ; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
 ; MIPS32-LABEL: passFpConstArg
-; MIPS32:       mfc1    a2,$f1
-; MIPS32:       mfc1    a3,$f0
+; MIPS32:       mfc1    a2,$f{{[0-9]+}}
+; MIPS32:       mfc1    a3,$f{{[0-9]+}}
 ; MIPS32:       li      a1,123
 ; MIPS32:       jal     {{.*}}  ignoreFpArgsNoInline
 
 define internal i32 @passFp32ConstArg(float %a) {
 entry:
   %call = call i32 @ignoreFp32ArgsNoInline(float %a, i32 123, float 2.0)
   ret i32 %call
 }
 ; CHECK-LABEL: passFp32ConstArg
 ; CHECK: mov DWORD PTR [esp+0x4],0x7b
@@ skipping 26 matching lines @@
 ; MIPS32:       mov.d   $f0,$f12
 ; MIPS32:       jr      ra
 
 define internal float @returnFloatConst() {
 entry:
   ret float 0x3FF3AE1480000000
 }
 ; CHECK-LABEL: returnFloatConst
 ; CHECK: fld
 ; MIPS32-LABEL: returnFloatConst
-; MIPS32:       lui     v0,0x0     160: R_MIPS_HI16     .L$float$3f9d70a4
-; MIPS32:       lwc1    $f0,0(v0)  164: R_MIPS_LO16     .L$float$3f9d70a4
+; MIPS32:       lui     v0,0x0    {{.*}} .L$float$3f9d70a4
+; MIPS32:       lwc1    $f0,0(v0) {{.*}} .L$float$3f9d70a4
 ; MIPS32:       jr      ra
 
 define internal double @returnDoubleConst() {
 entry:
   ret double 1.230000e+00
 }
 ; CHECK-LABEL: returnDoubleConst
 ; CHECK: fld
 ; MIPS32-LABEL: returnDoubleConst
-; MIPS32:       lui     v0,0x0     170: R_MIPS_HI16  .L$double$3ff3ae147ae147ae
-; MIPS32:       ldc1    $f0,0(v0)  174: R_MIPS_LO16  .L$double$3ff3ae147ae147ae
+; MIPS32:       lui     v0,0x0     {{.*}}  .L$double$3ff3ae147ae147ae
+; MIPS32:       ldc1    $f0,0(v0)  {{.*}}  .L$double$3ff3ae147ae147ae
 ; MIPS32:       jr      ra