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Issue 2619943003: [SubZero] Fix code generation issues occurred in Cross-test and PNaCL smoke-tests (Closed)
Patch Set: Addressed review comments Created 3 years, 11 months ago
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1 ; Trivial smoke test of bitcast between integer and FP types. 1 ; Trivial smoke test of bitcast between integer and FP types.
2 2
3 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s 3 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
4 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s 4 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
5 5
6 ; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \ 6 ; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \
7 ; RUN: --target arm32 -i %s --args -O2 \ 7 ; RUN: --target arm32 -i %s --args -O2 \
8 ; RUN: | %if --need=target_ARM32 --command FileCheck %s \ 8 ; RUN: | %if --need=target_ARM32 --command FileCheck %s \
9 ; RUN: --check-prefix=ARM32 9 ; RUN: --check-prefix=ARM32
10 10
(...skipping 47 matching lines...) Expand 10 before | Expand all | Expand 10 after
58 define internal i64 @cast_d2ll(double %d) { 58 define internal i64 @cast_d2ll(double %d) {
59 entry: 59 entry:
60 %v0 = bitcast double %d to i64 60 %v0 = bitcast double %d to i64
61 ret i64 %v0 61 ret i64 %v0
62 } 62 }
63 ; CHECK-LABEL: cast_d2ll 63 ; CHECK-LABEL: cast_d2ll
64 ; CHECK: mov edx 64 ; CHECK: mov edx
65 ; ARM32-LABEL: cast_d2ll 65 ; ARM32-LABEL: cast_d2ll
66 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, d{{[0-9]+}} 66 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, d{{[0-9]+}}
67 ; MIPS32-LABEL: cast_d2ll 67 ; MIPS32-LABEL: cast_d2ll
68 ; MIPS32-O2: mfc1 $v1, $f{{[0-9]+}} 68 ; MIPS32-O2: swc1 $f13, {{.*}}
69 ; MIPS32-O2: mfc1 $v0, $f{{[0-9]+}} 69 ; MIPS32-O2: swc1 $f12, {{.*}}
70 ; MIPS32-O2: lw $v0, {{.*}}
71 ; MIPS32-O2: lw $v1, {{.*}}
70 ; MIPS32-OM1: sdc1 72 ; MIPS32-OM1: sdc1
71 ; MIPS32-OM1: lw 73 ; MIPS32-OM1: lw
72 ; MIPS32-OM1: lw 74 ; MIPS32-OM1: lw
73 75
74 define internal i64 @cast_d2ll_const() { 76 define internal i64 @cast_d2ll_const() {
75 entry: 77 entry:
76 %v0 = bitcast double 0x12345678901234 to i64 78 %v0 = bitcast double 0x12345678901234 to i64
77 ret i64 %v0 79 ret i64 %v0
78 } 80 }
79 ; CHECK-LABEL: cast_d2ll_const 81 ; CHECK-LABEL: cast_d2ll_const
80 ; CHECK: mov e{{..}},{{(DWORD PTR )?}}ds:0x0 {{.*}} {{.*}}0012345678901234 82 ; CHECK: mov e{{..}},{{(DWORD PTR )?}}ds:0x0 {{.*}} {{.*}}0012345678901234
81 ; CHECK: mov e{{..}},{{(DWORD PTR )?}}ds:0x4 {{.*}} {{.*}}0012345678901234 83 ; CHECK: mov e{{..}},{{(DWORD PTR )?}}ds:0x4 {{.*}} {{.*}}0012345678901234
82 ; ARM32-LABEL: cast_d2ll_const 84 ; ARM32-LABEL: cast_d2ll_const
83 ; ARM32-DAG: movw [[ADDR:r[0-9]+]], #{{.*_MOVW_}} 85 ; ARM32-DAG: movw [[ADDR:r[0-9]+]], #{{.*_MOVW_}}
84 ; ARM32-DAG: movt [[ADDR]], #{{.*_MOVT_}} 86 ; ARM32-DAG: movt [[ADDR]], #{{.*_MOVT_}}
85 ; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}} 87 ; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}
86 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, [[DREG]] 88 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, [[DREG]]
87 ; MIPS32-LABEL: cast_d2ll_const 89 ; MIPS32-LABEL: cast_d2ll_const
88 ; MIPS32: lui {{.*}}, %hi(.L$double$0012345678901234) 90 ; MIPS32: lui {{.*}}, %hi(.L$double$0012345678901234)
89 ; MIPS32: ldc1 {{.*}}, %lo(.L$double$0012345678901234)({{.*}}) 91 ; MIPS32: ldc1 {{.*}}, %lo(.L$double$0012345678901234)({{.*}})
90 ; MIPS32-O2: mfc1 $v1, $f{{[0-9]+}} 92 ; MIPS32: swc1 $f{{[0-9]+}}, {{.*}}
91 ; MIPS32-O2: mfc1 $v0, $f{{[0-9]+}} 93 ; MIPS32: swc1 $f{{[0-9]+}}, {{.*}}
92 ; MIPS32-OM1: mfc1 94 ; MIPS32: lw $v0, {{.*}}
93 ; MIPS32-OM1: mfc1 95 ; MIPS32: lw $v1, {{.*}}
94 ; MIPS32-OM1: lw
95 ; MIPS32-OM1: lw
96 96
97 define internal double @cast_ll2d(i64 %ll) { 97 define internal double @cast_ll2d(i64 %ll) {
98 entry: 98 entry:
99 %v0 = bitcast i64 %ll to double 99 %v0 = bitcast i64 %ll to double
100 ret double %v0 100 ret double %v0
101 } 101 }
102 ; CHECK-LABEL: cast_ll2d 102 ; CHECK-LABEL: cast_ll2d
103 ; CHECK: fld QWORD PTR 103 ; CHECK: fld QWORD PTR
104 ; ARM32-LABEL: cast_ll2d 104 ; ARM32-LABEL: cast_ll2d
105 ; ARM32: vmov d{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} 105 ; ARM32: vmov d{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
(...skipping 20 matching lines...) Expand all
126 ; ARM32: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] 126 ; ARM32: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]
127 ; MIPS32-LABEL: cast_ll2d_const 127 ; MIPS32-LABEL: cast_ll2d_const
128 ; MIPS32: lui {{.*}}, 29646 128 ; MIPS32: lui {{.*}}, 29646
129 ; MIPS32: ori {{.*}}, {{.*}}, 12274 129 ; MIPS32: ori {{.*}}, {{.*}}, 12274
130 ; MIPS32: addiu {{.*}}, $zero, 2874 130 ; MIPS32: addiu {{.*}}, $zero, 2874
131 ; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}} 131 ; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}}
132 ; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}} 132 ; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}}
133 ; MIPS32-OM1: sw 133 ; MIPS32-OM1: sw
134 ; MIPS32-OM1: sw 134 ; MIPS32-OM1: sw
135 ; MIPS32-OM1: ldc1 135 ; MIPS32-OM1: ldc1
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