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Side by Side Diff: tests_lit/llvm2ice_tests/alloc.ll

Issue 2619943003: [SubZero] Fix code generation issues occurred in Cross-test and PNaCL smoke-tests (Closed)
Patch Set: Addressed review comments Created 3 years, 11 months ago
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1 ; This is a basic test of the alloca instruction. 1 ; This is a basic test of the alloca instruction.
2 2
3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
4 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \ 4 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
5 ; RUN: | %if --need=target_X8632 --command FileCheck %s 5 ; RUN: | %if --need=target_X8632 --command FileCheck %s
6 6
7 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 7 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
8 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ 8 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
9 ; RUN: | %if --need=target_X8632 --command FileCheck \ 9 ; RUN: | %if --need=target_X8632 --command FileCheck \
10 ; RUN: --check-prefix CHECK-OPTM1 %s 10 ; RUN: --check-prefix CHECK-OPTM1 %s
(...skipping 44 matching lines...) Expand 10 before | Expand all | Expand 10 after
55 ; CHECK-OPTM1: sub esp,0x1a0 55 ; CHECK-OPTM1: sub esp,0x1a0
56 ; CHECK-OPTM1: mov DWORD PTR [esp],eax 56 ; CHECK-OPTM1: mov DWORD PTR [esp],eax
57 ; CHECK-OPTM1: call {{.*}} R_{{.*}} f1 57 ; CHECK-OPTM1: call {{.*}} R_{{.*}} f1
58 58
59 ; ARM32-LABEL: fixed_416_align_16 59 ; ARM32-LABEL: fixed_416_align_16
60 ; ARM32-OPT2: sub sp, sp, #428 60 ; ARM32-OPT2: sub sp, sp, #428
61 ; ARM32-OPTM1: sub sp, sp, #416 61 ; ARM32-OPTM1: sub sp, sp, #416
62 ; ARM32: bl {{.*}} R_{{.*}} f1 62 ; ARM32: bl {{.*}} R_{{.*}} f1
63 63
64 ; MIPS32-LABEL: fixed_416_align_16 64 ; MIPS32-LABEL: fixed_416_align_16
65 ; MIPS32-OPT2: addiu sp,sp,-436 65 ; MIPS32-OPT2: addiu sp,sp,-448
66 ; MIPS32-OPT2: addiu a0,sp,16 66 ; MIPS32-OPT2: addiu a0,sp,16
67 ; MIPS32-OPTM1: addiu sp,sp,-456 67 ; MIPS32-OPTM1: addiu sp,sp,-464
68 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,16 68 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,16
69 ; MIPS32-OPTM1: sw [[REG]],{{.*}} 69 ; MIPS32-OPTM1: sw [[REG]],{{.*}}
70 ; MIPS32-OPTM1: lw a0,{{.*}} 70 ; MIPS32-OPTM1: lw a0,{{.*}}
71 ; MIPS32: jal {{.*}} R_{{.*}} f1 71 ; MIPS32: jal {{.*}} R_{{.*}} f1
72 72
73 define internal void @fixed_416_align_32(i32 %n) { 73 define internal void @fixed_416_align_32(i32 %n) {
74 entry: 74 entry:
75 %array = alloca i8, i32 400, align 32 75 %array = alloca i8, i32 400, align 32
76 %__2 = ptrtoint i8* %array to i32 76 %__2 = ptrtoint i8* %array to i32
77 call void @f1(i32 %__2) 77 call void @f1(i32 %__2)
78 ret void 78 ret void
79 } 79 }
80 ; CHECK-LABEL: fixed_416_align_32 80 ; CHECK-LABEL: fixed_416_align_32
81 ; CHECK: push ebp 81 ; CHECK: push ebp
82 ; CHECK-NEXT: mov ebp,esp 82 ; CHECK-NEXT: mov ebp,esp
83 ; CHECK: sub esp,0x1b8 83 ; CHECK: sub esp,0x1b8
84 ; CHECK: and esp,0xffffffe0 84 ; CHECK: and esp,0xffffffe0
85 ; CHECK: lea eax,[esp+0x10] 85 ; CHECK: lea eax,[esp+0x10]
86 ; CHECK: mov DWORD PTR [esp],eax 86 ; CHECK: mov DWORD PTR [esp],eax
87 ; CHECK: call {{.*}} R_{{.*}} f1 87 ; CHECK: call {{.*}} R_{{.*}} f1
88 88
89 ; ARM32-LABEL: fixed_416_align_32 89 ; ARM32-LABEL: fixed_416_align_32
90 ; ARM32-OPT2: sub sp, sp, #424 90 ; ARM32-OPT2: sub sp, sp, #424
91 ; ARM32-OPTM1: sub sp, sp, #416 91 ; ARM32-OPTM1: sub sp, sp, #416
92 ; ARM32: bic sp, sp, #31 92 ; ARM32: bic sp, sp, #31
93 ; ARM32: bl {{.*}} R_{{.*}} f1 93 ; ARM32: bl {{.*}} R_{{.*}} f1
94 94
95 ; MIPS32-LABEL: fixed_416_align_32 95 ; MIPS32-LABEL: fixed_416_align_32
96 ; MIPS32-OPT2: addiu sp,sp,-440 96 ; MIPS32-OPT2: addiu sp,sp,-448
97 ; MIPS32-OPT2: addiu a0,sp,32 97 ; MIPS32-OPT2: addiu a0,sp,16
98 ; MIPS32-OPTM1: addiu sp,sp,-456 98 ; MIPS32-OPTM1: addiu sp,sp,-464
99 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,32 99 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,32
100 ; MIPS32-OPTM1: sw [[REG]],{{.*}} 100 ; MIPS32-OPTM1: sw [[REG]],{{.*}}
101 ; MIPS32-OPTM1: lw a0,{{.*}} 101 ; MIPS32-OPTM1: lw a0,{{.*}}
102 ; MIPS32: jal {{.*}} R_{{.*}} f1 102 ; MIPS32: jal {{.*}} R_{{.*}} f1
103 103
104 ; Show that the amount to allocate will be rounded up. 104 ; Show that the amount to allocate will be rounded up.
105 define internal void @fixed_351_align_16(i32 %n) { 105 define internal void @fixed_351_align_16(i32 %n) {
106 entry: 106 entry:
107 %array = alloca i8, i32 351, align 16 107 %array = alloca i8, i32 351, align 16
108 %__2 = ptrtoint i8* %array to i32 108 %__2 = ptrtoint i8* %array to i32
(...skipping 11 matching lines...) Expand all
120 ; CHECK-OPTM1: sub esp,0x160 120 ; CHECK-OPTM1: sub esp,0x160
121 ; CHECK-OPTM1: mov DWORD PTR [esp],eax 121 ; CHECK-OPTM1: mov DWORD PTR [esp],eax
122 ; CHECK-OPTM1: call {{.*}} R_{{.*}} f1 122 ; CHECK-OPTM1: call {{.*}} R_{{.*}} f1
123 123
124 ; ARM32-LABEL: fixed_351_align_16 124 ; ARM32-LABEL: fixed_351_align_16
125 ; ARM32-OPT2: sub sp, sp, #364 125 ; ARM32-OPT2: sub sp, sp, #364
126 ; ARM32-OPTM1: sub sp, sp, #352 126 ; ARM32-OPTM1: sub sp, sp, #352
127 ; ARM32: bl {{.*}} R_{{.*}} f1 127 ; ARM32: bl {{.*}} R_{{.*}} f1
128 128
129 ; MIPS32-LABEL: fixed_351_align_16 129 ; MIPS32-LABEL: fixed_351_align_16
130 ; MIPS32-OPT2: addiu sp,sp,-372 130 ; MIPS32-OPT2: addiu sp,sp,-384
131 ; MIPS32-OPT2: addiu a0,sp,16 131 ; MIPS32-OPT2: addiu a0,sp,16
132 ; MIPS32-OPTM1: addiu sp,sp,-392 132 ; MIPS32-OPTM1: addiu sp,sp,-400
133 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,16 133 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,16
134 ; MIPS32-OPTM1: sw [[REG]],{{.*}} 134 ; MIPS32-OPTM1: sw [[REG]],{{.*}}
135 ; MIPS32-OPTM1: lw a0,{{.*}} 135 ; MIPS32-OPTM1: lw a0,{{.*}}
136 ; MIPS32: jal {{.*}} R_{{.*}} f1 136 ; MIPS32: jal {{.*}} R_{{.*}} f1
137 137
138 define internal void @fixed_351_align_32(i32 %n) { 138 define internal void @fixed_351_align_32(i32 %n) {
139 entry: 139 entry:
140 %array = alloca i8, i32 351, align 32 140 %array = alloca i8, i32 351, align 32
141 %__2 = ptrtoint i8* %array to i32 141 %__2 = ptrtoint i8* %array to i32
142 call void @f1(i32 %__2) 142 call void @f1(i32 %__2)
143 ret void 143 ret void
144 } 144 }
145 ; CHECK-LABEL: fixed_351_align_32 145 ; CHECK-LABEL: fixed_351_align_32
146 ; CHECK: push ebp 146 ; CHECK: push ebp
147 ; CHECK-NEXT: mov ebp,esp 147 ; CHECK-NEXT: mov ebp,esp
148 ; CHECK: sub esp,0x178 148 ; CHECK: sub esp,0x178
149 ; CHECK: and esp,0xffffffe0 149 ; CHECK: and esp,0xffffffe0
150 ; CHECK: lea eax,[esp+0x10] 150 ; CHECK: lea eax,[esp+0x10]
151 ; CHECK: mov DWORD PTR [esp],eax 151 ; CHECK: mov DWORD PTR [esp],eax
152 ; CHECK: call {{.*}} R_{{.*}} f1 152 ; CHECK: call {{.*}} R_{{.*}} f1
153 153
154 ; ARM32-LABEL: fixed_351_align_32 154 ; ARM32-LABEL: fixed_351_align_32
155 ; ARM32-OPT2: sub sp, sp, #360 155 ; ARM32-OPT2: sub sp, sp, #360
156 ; ARM32-OPTM1: sub sp, sp, #352 156 ; ARM32-OPTM1: sub sp, sp, #352
157 ; ARM32: bic sp, sp, #31 157 ; ARM32: bic sp, sp, #31
158 ; ARM32: bl {{.*}} R_{{.*}} f1 158 ; ARM32: bl {{.*}} R_{{.*}} f1
159 159
160 ; MIPS32-LABEL: fixed_351_align_32 160 ; MIPS32-LABEL: fixed_351_align_32
161 ; MIPS32-OPT2: addiu sp,sp,-376 161 ; MIPS32-OPT2: addiu sp,sp,-384
162 ; MIPS32-OPT2: addiu a0,sp,32 162 ; MIPS32-OPT2: addiu a0,sp,16
163 ; MIPS32-OPTM1: addiu sp,sp,-392 163 ; MIPS32-OPTM1: addiu sp,sp,-400
164 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,32 164 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,32
165 ; MIPS32-OPTM1: sw [[REG]],{{.*}} 165 ; MIPS32-OPTM1: sw [[REG]],{{.*}}
166 ; MIPS32-OPTM1: lw a0,{{.*}} 166 ; MIPS32-OPTM1: lw a0,{{.*}}
167 ; MIPS32: jal {{.*}} R_{{.*}} f1 167 ; MIPS32: jal {{.*}} R_{{.*}} f1
168 168
169 declare void @f1(i32 %ignored) 169 declare void @f1(i32 %ignored)
170 170
171 declare void @f2(i32 %ignored) 171 declare void @f2(i32 %ignored)
172 172
173 define internal void @variable_n_align_16(i32 %n) { 173 define internal void @variable_n_align_16(i32 %n) {
(...skipping 221 matching lines...) Expand 10 before | Expand all | Expand 10 after
395 %p1 = bitcast i8* %a1 to i32* 395 %p1 = bitcast i8* %a1 to i32*
396 %p2 = bitcast i8* %a2 to i32* 396 %p2 = bitcast i8* %a2 to i32*
397 %p3 = bitcast i8* %a3 to i32* 397 %p3 = bitcast i8* %a3 to i32*
398 store i32 %arg, i32* %p1, align 1 398 store i32 %arg, i32* %p1, align 1
399 store i32 %arg, i32* %p2, align 1 399 store i32 %arg, i32* %p2, align 1
400 store i32 %arg, i32* %p3, align 1 400 store i32 %arg, i32* %p3, align 1
401 ret void 401 ret void
402 } 402 }
403 ; CHECK-LABEL: var_with_frameptr 403 ; CHECK-LABEL: var_with_frameptr
404 ; CHECK: mov ebp,esp 404 ; CHECK: mov ebp,esp
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