[SubZero] Fix code generation issues occurred in Cross-test and PNaCL smoke-tests

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 79 matching lines @@
 
 // Stack alignment
 constexpr uint32_t MIPS32_STACK_ALIGNMENT_BYTES = 16;
 
 // Value is in bytes. Return Value adjusted to the next highest multiple of the
 // stack alignment required for the given type.
 uint32_t applyStackAlignmentTy(uint32_t Value, Type Ty) {
   size_t typeAlignInBytes = typeWidthInBytes(Ty);
   // Vectors are stored on stack with the same alignment as that of int type
   if (isVectorType(Ty))
-    typeAlignInBytes = typeWidthInBytes(IceType_i32);
+    typeAlignInBytes = typeWidthInBytes(IceType_i64);
   return Utils::applyAlignment(Value, typeAlignInBytes);
 }
 
 // Value is in bytes. Return Value adjusted to the next highest multiple of the
 // stack alignment.
 uint32_t applyStackAlignment(uint32_t Value) {
   return Utils::applyAlignment(Value, MIPS32_STACK_ALIGNMENT_BYTES);
 }
 
 } // end of anonymous namespace
@@ skipping 122 matching lines @@
     PartialOnStack = true;
   }
   for (SizeT i = 0, NumArgs = Call->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = legalizeUndef(Call->getArg(i));
     const Type Ty = Arg->getType();
     RegNumT RegNum;
     if (CC.argInReg(Ty, i, &RegNum)) {
       // If PartialOnStack is true and if this is a vector type then last two
       // elements are on stack
       if (PartialOnStack && isVectorType(Ty)) {
-        OutArgsSizeBytes = applyStackAlignmentTy(OutArgsSizeBytes, IceType_i32);
+        OutArgsSizeBytes = applyStackAlignmentTy(OutArgsSizeBytes, IceType_i64);
         OutArgsSizeBytes += typeWidthInBytesOnStack(IceType_i32) * 2;
       }
       continue;
     }
     OutArgsSizeBytes = applyStackAlignmentTy(OutArgsSizeBytes, Ty);
     OutArgsSizeBytes += typeWidthInBytesOnStack(Ty);
   }
   // Add size of argument save area
   constexpr int BytesPerStackArg = 4;
   OutArgsSizeBytes += MIPS32_MAX_GPR_ARG * BytesPerStackArg;
@@ skipping 726 matching lines @@
     //     Context.insert(InstFakeDef::create(Func, Reg));
     // This is in order to ensure that the live range of Reg is not
     // overestimated.  If the constant being lowered is a 64 bit value,
     // then the result should be split and the lo and hi components will
     // need to go in uninitialized registers.
     if (isVectorType(Ty)) {
       Variable *Var = makeReg(Ty, RegNum);
       auto *Reg = llvm::cast<VariableVecOn32>(Var);
       Reg->initVecElement(Func);
       auto *Zero = getZero();
-      Context.insert<InstFakeDef>(Zero);
       for (Variable *Var : Reg->getContainers()) {
         _mov(Var, Zero);
       }
       return Reg;
     }
     return Ctx->getConstantZero(Ty);
   }
   return From;
 }
 
@@ skipping 467 matching lines @@
 
   // RegClasses is a tuple of
   //
   // <First Register in Class, Last Register in Class, Vector of Save Registers>
   //
   // We use this tuple to figure out which register we should save/restore
   // during
   // prolog/epilog.
   using RegClassType = std::tuple<uint32_t, uint32_t, VarList *>;
   const RegClassType RegClass = RegClassType(
-      RegMIPS32::Reg_GPR_First, RegMIPS32::Reg_GPR_Last, &PreservedGPRs);
+      RegMIPS32::Reg_GPR_First, RegMIPS32::Reg_FPR_Last, &PreservedGPRs);
   const uint32_t FirstRegInClass = std::get<0>(RegClass);
   const uint32_t LastRegInClass = std::get<1>(RegClass);
   VarList *const PreservedRegsInClass = std::get<2>(RegClass);
   for (uint32_t Reg = LastRegInClass; Reg > FirstRegInClass; Reg--) {
     if (!ToPreserve[Reg]) {
       continue;
     }
     ++NumCallee;
     Variable *PhysicalRegister = getPhysicalRegister(RegNumT::fromInt(Reg));
     PreservedRegsSizeBytes +=
@@ skipping 24 matching lines @@
     SpillAreaSizeBytes += MaxOutArgsSizeBytes * (VariableAllocaUsed ? 0 : 1);
   } else {
     SpillAreaSizeBytes = applyStackAlignment(
         SpillAreaSizeBytes +
         (VariableAllocaUsed ? VariableAllocaAlignBytes : MaxOutArgsSizeBytes));
   }
 
   // Combine fixed alloca with SpillAreaSize.
   SpillAreaSizeBytes += FixedAllocaSizeBytes;
 
-  TotalStackSizeBytes = PreservedRegsSizeBytes + SpillAreaSizeBytes;
+  TotalStackSizeBytes =
+      applyStackAlignment(PreservedRegsSizeBytes + SpillAreaSizeBytes);
 
   // Generate "addiu sp, sp, -TotalStackSizeBytes"
   if (TotalStackSizeBytes) {
     // Use the scratch register if needed to legalize the immediate.
     Sandboxer(this).addiu_sp(-TotalStackSizeBytes);
   }
 
   Ctx->statsUpdateFrameBytes(TotalStackSizeBytes);
 
   if (!PreservedGPRs.empty()) {
     uint32_t StackOffset = TotalStackSizeBytes;
     for (Variable *Var : *PreservedRegsInClass) {
-      Variable *PhysicalRegister = getPhysicalRegister(Var->getRegNum());
-      StackOffset -= typeWidthInBytesOnStack(PhysicalRegister->getType());
+      Type RegType;
+      if (RegMIPS32::isFPRReg(Var->getRegNum()))
+        RegType = IceType_f32;
+      else
+        RegType = IceType_i32;
+      auto *PhysicalRegister = makeReg(RegType, Var->getRegNum());
+      StackOffset -= typeWidthInBytesOnStack(RegType);
       Variable *SP = getPhysicalRegister(RegMIPS32::Reg_SP);
       OperandMIPS32Mem *MemoryLocation = OperandMIPS32Mem::create(
-          Func, IceType_i32, SP,
+          Func, RegType, SP,
           llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(StackOffset)));
       Sandboxer(this).sw(PhysicalRegister, MemoryLocation);
     }
   }
 
   Variable *FP = getPhysicalRegister(RegMIPS32::Reg_FP);
 
   // Generate "mov FP, SP" if needed.
   if (UsesFramePointer) {
     Variable *SP = getPhysicalRegister(RegMIPS32::Reg_SP);
@@ skipping 94 matching lines @@
     Context.insert<InstFakeUse>(SP);
     Sandboxer(this).reset_sp(FP);
   }
 
   VarList::reverse_iterator RIter, END;
 
   if (!PreservedGPRs.empty()) {
     uint32_t StackOffset = TotalStackSizeBytes - PreservedRegsSizeBytes;
     for (RIter = PreservedGPRs.rbegin(), END = PreservedGPRs.rend();
          RIter != END; ++RIter) {
-      Variable *PhysicalRegister = getPhysicalRegister((*RIter)->getRegNum());
+      Type RegType;
+      if (RegMIPS32::isFPRReg((*RIter)->getRegNum()))
+        RegType = IceType_f32;
+      else
+        RegType = IceType_i32;
+      auto *PhysicalRegister = makeReg(RegType, (*RIter)->getRegNum());
       Variable *SP = getPhysicalRegister(RegMIPS32::Reg_SP);
       OperandMIPS32Mem *MemoryLocation = OperandMIPS32Mem::create(
-          Func, IceType_i32, SP,
+          Func, RegType, SP,
           llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(StackOffset)));
       _lw(PhysicalRegister, MemoryLocation);
       StackOffset += typeWidthInBytesOnStack(PhysicalRegister->getType());
     }
   }
 
   if (TotalStackSizeBytes) {
     Sandboxer(this).addiu_sp(TotalStackSizeBytes);
   }
   if (!getFlags().getUseSandboxing())
@@ skipping 27 matching lines @@
         Target->_ori(ScratchReg, ScratchReg, LowerBits);
       Target->_addu(ScratchReg, ScratchReg, Base);
     } else {
       Target->_addiu(ScratchReg, Base, Offset);
     }
   }
 
   return ScratchReg;
 }
 
+void TargetMIPS32::PostLoweringLegalizer::legalizeMovFp(
+    InstMIPS32MovFP64ToI64 *MovInstr) {
+  Variable *Dest = MovInstr->getDest();
+  Operand *Src = MovInstr->getSrc(0);
+  const Type SrcTy = Src->getType();
+
+  if (Dest != nullptr && SrcTy == IceType_f64) {
+    int32_t Offset = Dest->getStackOffset();
+    auto *Base = Target->getPhysicalRegister(Target->getFrameOrStackReg());
+    OperandMIPS32Mem *TAddr = OperandMIPS32Mem::create(
+        Target->Func, IceType_f32, Base,
+        llvm::cast<ConstantInteger32>(Target->Ctx->getConstantInt32(Offset)));
+    OperandMIPS32Mem *Addr = legalizeMemOperand(TAddr);
+    auto *SrcV = llvm::cast<Variable>(Src);
+    Variable *SrcR;
+    if (MovInstr->getInt64Part() == Int64_Lo) {
+      SrcR = Target->makeReg(
+          IceType_f32, RegMIPS32::get64PairFirstRegNum(SrcV->getRegNum()));
+    } else {
+      SrcR = Target->makeReg(
+          IceType_f32, RegMIPS32::get64PairSecondRegNum(SrcV->getRegNum()));
+    }
+    Sandboxer(Target).sw(SrcR, Addr);
+    if (MovInstr->isDestRedefined()) {
+      Target->_set_dest_redefined();
+    }
+    MovInstr->setDeleted();
+    return;
+  }
+
+  llvm::report_fatal_error("legalizeMovFp: Invalid operands");
+}
+
 void TargetMIPS32::PostLoweringLegalizer::legalizeMov(InstMIPS32Mov *MovInstr) {
   Variable *Dest = MovInstr->getDest();
   assert(Dest != nullptr);
   const Type DestTy = Dest->getType();
   assert(DestTy != IceType_i64);
 
   Operand *Src = MovInstr->getSrc(0);
   const Type SrcTy = Src->getType();
   (void)SrcTy;
   assert(SrcTy != IceType_i64);
@@ skipping 24 matching lines @@
           if (MovInstr->getDestHi() != nullptr && Dest != nullptr) {
             DstFPRHi = Target->makeReg(IceType_i32,
                                        MovInstr->getDestHi()->getRegNum());
             DstFPRLo = Target->makeReg(IceType_i32, Dest->getRegNum());
           } else {
             DstFPRHi = Target->makeReg(
                 IceType_i32, RegMIPS32::get64PairFirstRegNum(DRegNum));
             DstFPRLo = Target->makeReg(
                 IceType_i32, RegMIPS32::get64PairSecondRegNum(DRegNum));
           }
-          Target->_mov(DstFPRHi, SrcGPRLo);
-          Target->_mov(DstFPRLo, SrcGPRHi);
+          Target->_mov(DstFPRHi, SrcGPRHi);
+          Target->_mov(DstFPRLo, SrcGPRLo);
           Legalized = true;
         } else {
           Variable *SrcGPR = Target->makeReg(IceType_f32, SRegNum);
           Variable *DstFPR = Target->makeReg(IceType_i32, DRegNum);
           Target->_mov(DstFPR, SrcGPR);
           Legalized = true;
         }
       } else {
         // Dest is FPR and SrcR is GPR. Use mtc1.
         if (typeWidthInBytes(Dest->getType()) == 8) {
@@ skipping 91 matching lines @@
     }
 
     Target->Context.insert<InstFakeDef>(Dest);
     Legalized = true;
   } else if (auto *Var = llvm::dyn_cast<Variable>(Src)) {
     if (Var->isRematerializable()) {
       // This is equivalent to an x86 _lea(RematOffset(%esp/%ebp), Variable).
 
       // ExtraOffset is only needed for stack-pointer based frames as we have
       // to account for spill storage.
-      const int32_t ExtraOffset = (Var->getRegNum() == Target->getStackReg())
-                                      ? Target->getFrameFixedAllocaOffset()
-                                      : 0;
+      const int32_t ExtraOffset =
+          (Var->getRegNum() == Target->getFrameOrStackReg())
+              ? Target->getFrameFixedAllocaOffset()
+              : 0;
 
       const int32_t Offset = Var->getStackOffset() + ExtraOffset;
       Variable *Base = Target->getPhysicalRegister(Var->getRegNum());
       Variable *T = newBaseRegister(Base, Offset, Dest->getRegNum());
       Target->_mov(Dest, T);
       Legalized = true;
     } else {
       if (!Var->hasReg()) {
         // This is a _mov(Variable, Mem()), i.e., a load.
         const int32_t Offset = Var->getStackOffset();
@@ skipping 135 matching lines @@
       Operand *Src0 = NumSrcs < 1 ? nullptr : CurInstr->getSrc(0);
       Operand *Src1 = NumSrcs < 2 ? nullptr : CurInstr->getSrc(1);
       auto *Src0V = llvm::dyn_cast_or_null<Variable>(Src0);
       auto *Src0M = llvm::dyn_cast_or_null<OperandMIPS32Mem>(Src0);
       auto *Src1M = llvm::dyn_cast_or_null<OperandMIPS32Mem>(Src1);
       Variable *Dst = CurInstr->getDest();
       if (auto *MovInstr = llvm::dyn_cast<InstMIPS32Mov>(CurInstr)) {
         Legalizer.legalizeMov(MovInstr);
         continue;
       }
+      if (auto *MovInstr = llvm::dyn_cast<InstMIPS32MovFP64ToI64>(CurInstr)) {
+        Legalizer.legalizeMovFp(MovInstr);
+        continue;
+      }
       if (llvm::isa<InstMIPS32Sw>(CurInstr)) {
         if (auto *LegalMem = Legalizer.legalizeMemOperand(Src1M)) {
           Sandboxer(this).sw(Src0V, LegalMem);
           CurInstr->setDeleted();
         }
         continue;
       }
       if (llvm::isa<InstMIPS32Swc1>(CurInstr)) {
         if (auto *LegalMem = Legalizer.legalizeMemOperand(Src1M)) {
           _swc1(Src0V, LegalMem);
@@ skipping 570 matching lines @@
   }
 
   Variable *T = makeReg(Dest->getType());
   Variable *Src0R = legalizeToReg(Src0);
   Variable *Src1R = nullptr;
   uint32_t Value = 0;
   bool IsSrc1Imm16 = false;
 
   switch (Instr->getOp()) {
   case InstArithmetic::Add:
-  case InstArithmetic::And:
-  case InstArithmetic::Or:
-  case InstArithmetic::Xor:
-  case InstArithmetic::Sub:
-  case InstArithmetic::Shl:
-  case InstArithmetic::Lshr:
-  case InstArithmetic::Ashr: {
+  case InstArithmetic::Sub: {
     auto *Const32 = llvm::dyn_cast<ConstantInteger32>(Src1);
     if (Const32 != nullptr && isInt<16>(int32_t(Const32->getValue()))) {
       IsSrc1Imm16 = true;
       Value = Const32->getValue();
     } else {
+      Src1R = legalizeToReg(Src1);
+    }
+    break;
+  }
+  case InstArithmetic::And:
+  case InstArithmetic::Or:
+  case InstArithmetic::Xor:
+  case InstArithmetic::Shl:
+  case InstArithmetic::Lshr:
+  case InstArithmetic::Ashr: {
+    auto *Const32 = llvm::dyn_cast<ConstantInteger32>(Src1);
+    if (Const32 != nullptr && llvm::isUInt<16>(uint32_t(Const32->getValue()))) {
+      IsSrc1Imm16 = true;
+      Value = Const32->getValue();
+    } else {
       Src1R = legalizeToReg(Src1);
     }
     break;
   }
   default:
     Src1R = legalizeToReg(Src1);
     break;
   }
   constexpr uint32_t DivideByZeroTrapCode = 7;
 
   switch (Instr->getOp()) {
   case InstArithmetic::_num:
     break;
-  case InstArithmetic::Add:
+  case InstArithmetic::Add: {
+    auto *T0R = Src0R;
+    auto *T1R = Src1R;
+    if (Dest->getType() != IceType_i32) {
+      T0R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Sext, T0R, Src0R));
+      if (!IsSrc1Imm16) {
+        T1R = makeReg(IceType_i32);
+        lowerCast(InstCast::create(Func, InstCast::Sext, T1R, Src1R));
+      }
+    }
     if (IsSrc1Imm16) {
-      _addiu(T, Src0R, Value);
+      _addiu(T, T0R, Value);
     } else {
-      _addu(T, Src0R, Src1R);
+      _addu(T, T0R, T1R);
     }
     _mov(Dest, T);
     return;
+  }
   case InstArithmetic::And:
     if (IsSrc1Imm16) {
       _andi(T, Src0R, Value);
     } else {
       _and(T, Src0R, Src1R);
     }
     _mov(Dest, T);
     return;
   case InstArithmetic::Or:
     if (IsSrc1Imm16) {
       _ori(T, Src0R, Value);
     } else {
       _or(T, Src0R, Src1R);
     }
     _mov(Dest, T);
     return;
   case InstArithmetic::Xor:
     if (IsSrc1Imm16) {
       _xori(T, Src0R, Value);
     } else {
       _xor(T, Src0R, Src1R);
     }
     _mov(Dest, T);
     return;
-  case InstArithmetic::Sub:
+  case InstArithmetic::Sub: {
+    auto *T0R = Src0R;
+    auto *T1R = Src1R;
+    if (Dest->getType() != IceType_i32) {
+      T0R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Sext, T0R, Src0R));
+      if (!IsSrc1Imm16) {
+        T1R = makeReg(IceType_i32);
+        lowerCast(InstCast::create(Func, InstCast::Sext, T1R, Src1R));
+      }
+    }
     if (IsSrc1Imm16) {
-      _addiu(T, Src0R, -Value);
+      _addiu(T, T0R, -Value);
     } else {
-      _subu(T, Src0R, Src1R);
+      _subu(T, T0R, T1R);
     }
     _mov(Dest, T);
     return;
+  }
   case InstArithmetic::Mul: {
     _mul(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Shl: {
     if (IsSrc1Imm16) {
       _sll(T, Src0R, Value);
     } else {
       _sllv(T, Src0R, Src1R);
@@ skipping 14 matching lines @@
     }
     if (IsSrc1Imm16) {
       _srl(T, T0R, Value);
     } else {
       _srlv(T, T0R, T1R);
     }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Ashr: {
+    auto *T0R = Src0R;
+    auto *T1R = Src1R;
+    if (Dest->getType() != IceType_i32) {
+      T0R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Sext, T0R, Src0R));
+      if (!IsSrc1Imm16) {
+        T1R = makeReg(IceType_i32);
+        lowerCast(InstCast::create(Func, InstCast::Sext, T1R, Src1R));
+      }
+    }
     if (IsSrc1Imm16) {
-      _sra(T, Src0R, Value);
+      _sra(T, T0R, Value);
     } else {
-      _srav(T, Src0R, Src1R);
+      _srav(T, T0R, T1R);
     }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Udiv: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
     auto *T0R = Src0R;
     auto *T1R = Src1R;
     if (Dest->getType() != IceType_i32) {
       T0R = makeReg(IceType_i32);
       lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
       T1R = makeReg(IceType_i32);
       lowerCast(InstCast::create(Func, InstCast::Zext, T1R, Src1R));
     }
     _divu(T_Zero, T0R, T1R);
     _teq(T1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
     _mflo(T, T_Zero);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Sdiv: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
-    _div(T_Zero, Src0R, Src1R);
-    _teq(Src1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
+    auto *T0R = Src0R;
+    auto *T1R = Src1R;
+    if (Dest->getType() != IceType_i32) {
+      T0R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Sext, T0R, Src0R));
+      T1R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Sext, T1R, Src1R));
+    }
+    _div(T_Zero, T0R, T1R);
+    _teq(T1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
     _mflo(T, T_Zero);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Urem: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
     auto *T0R = Src0R;
     auto *T1R = Src1R;
     if (Dest->getType() != IceType_i32) {
       T0R = makeReg(IceType_i32);
       lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
       T1R = makeReg(IceType_i32);
       lowerCast(InstCast::create(Func, InstCast::Zext, T1R, Src1R));
     }
     _divu(T_Zero, T0R, T1R);
     _teq(T1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
     _mfhi(T, T_Zero);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Srem: {
     auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
-    _div(T_Zero, Src0R, Src1R);
-    _teq(Src1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
+    auto *T0R = Src0R;
+    auto *T1R = Src1R;
+    if (Dest->getType() != IceType_i32) {
+      T0R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Sext, T0R, Src0R));
+      T1R = makeReg(IceType_i32);
+      lowerCast(InstCast::create(Func, InstCast::Sext, T1R, Src1R));
+    }
+    _div(T_Zero, T0R, T1R);
+    _teq(T1R, T_Zero, DivideByZeroTrapCode); // Trap if divide-by-zero
     _mfhi(T, T_Zero);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Fadd: {
     if (DestTy == IceType_f32) {
       _add_s(T, Src0R, Src1R);
       _mov(Dest, T);
       return;
     }
@@ skipping 126 matching lines @@
     Variable *Src0R = nullptr;
     Variable *Src1R = nullptr;
     Variable *Src0HiR = nullptr;
     Variable *Src1HiR = nullptr;
     if (Src0Ty == IceType_i64) {
       Src0R = legalizeToReg(loOperand(Src0));
       Src1R = legalizeToReg(loOperand(Src1));
       Src0HiR = legalizeToReg(hiOperand(Src0));
       Src1HiR = legalizeToReg(hiOperand(Src1));
     } else {
-      Src0R = legalizeToReg(Src0);
-      Src1R = legalizeToReg(Src1);
+      auto *Src0RT = legalizeToReg(Src0);
+      auto *Src1RT = legalizeToReg(Src1);
+      // Sign/Zero extend the source operands
+      if (Src0Ty != IceType_i32) {
+        InstCast::OpKind CastKind;
+        switch (CompareInst->getCondition()) {
+        case InstIcmp::Eq:
+        case InstIcmp::Ne:
+        case InstIcmp::Sgt:
+        case InstIcmp::Sge:
+        case InstIcmp::Slt:
+        case InstIcmp::Sle:
+          CastKind = InstCast::Sext;
+          break;
+        default:
+          CastKind = InstCast::Zext;
+          break;
+        }
+        Src0R = makeReg(IceType_i32);
+        Src1R = makeReg(IceType_i32);
+        lowerCast(InstCast::create(Func, CastKind, Src0R, Src0RT));
+        lowerCast(InstCast::create(Func, CastKind, Src1R, Src1RT));
+      } else {
+        Src0R = Src0RT;
+        Src1R = Src1RT;
+      }
     }
     auto *DestT = makeReg(IceType_i32);
 
     switch (CompareInst->getCondition()) {
     default:
       llvm_unreachable("unexpected condition");
       return;
     case InstIcmp::Eq: {
       if (Src0Ty == IceType_i64) {
         auto *T1 = I32Reg();
@@ skipping 217 matching lines @@
     Operand *Arg = legalizeUndef(Instr->getArg(i));
     const Type Ty = Arg->getType();
     bool InReg = false;
     RegNumT Reg;
 
     InReg = CC.argInReg(Ty, i, &Reg);
 
     if (!InReg) {
       if (isVectorType(Ty)) {
         auto *ArgVec = llvm::cast<VariableVecOn32>(Arg);
+        ParameterAreaSizeBytes =
+            applyStackAlignmentTy(ParameterAreaSizeBytes, IceType_i64);
         for (Variable *Elem : ArgVec->getContainers()) {
-          ParameterAreaSizeBytes =
-              applyStackAlignmentTy(ParameterAreaSizeBytes, IceType_i32);
           StackArgs.push_back(std::make_pair(Elem, ParameterAreaSizeBytes));
           ParameterAreaSizeBytes += typeWidthInBytesOnStack(IceType_i32);
         }
       } else {
         ParameterAreaSizeBytes =
             applyStackAlignmentTy(ParameterAreaSizeBytes, Ty);
         StackArgs.push_back(std::make_pair(Arg, ParameterAreaSizeBytes));
         ParameterAreaSizeBytes += typeWidthInBytesOnStack(Ty);
       }
       ++ArgNum;
@@ skipping 12 matching lines @@
       Operand *Elem3 = ArgVec->getContainers()[3];
       // First argument is passed in $4:$5:$6:$7
       // Second and rest arguments are passed in $6:$7:stack:stack
       if (ArgNum == 0) {
         GPRArgs.push_back(
             std::make_pair(Elem2, RegNumT::fixme((unsigned)Reg + 2)));
         GPRArgs.push_back(
             std::make_pair(Elem3, RegNumT::fixme((unsigned)Reg + 3)));
       } else {
         ParameterAreaSizeBytes =
-            applyStackAlignmentTy(ParameterAreaSizeBytes, IceType_i32);
+            applyStackAlignmentTy(ParameterAreaSizeBytes, IceType_i64);
         StackArgs.push_back(std::make_pair(Elem2, ParameterAreaSizeBytes));
         ParameterAreaSizeBytes += typeWidthInBytesOnStack(IceType_i32);
-        ParameterAreaSizeBytes =
-            applyStackAlignmentTy(ParameterAreaSizeBytes, IceType_i32);
         StackArgs.push_back(std::make_pair(Elem3, ParameterAreaSizeBytes));
         ParameterAreaSizeBytes += typeWidthInBytesOnStack(IceType_i32);
       }
     } else if (Ty == IceType_i64) {
       Operand *Lo = loOperand(Arg);
       Operand *Hi = hiOperand(Arg);
       GPRArgs.push_back(
           std::make_pair(Lo, RegMIPS32::get64PairFirstRegNum(Reg)));
       GPRArgs.push_back(
           std::make_pair(Hi, RegMIPS32::get64PairSecondRegNum(Reg)));
@@ skipping 280 matching lines @@
         _mov(Dest, T);
       }
     }
     break;
   }
   case InstCast::Trunc: {
     if (Src0Ty == IceType_i64)
       Src0 = loOperand(Src0);
     Variable *Src0R = legalizeToReg(Src0);
     Variable *T = makeReg(DestTy);
-    _mov(T, Src0R);
+    switch (DestTy) {
+    case IceType_i1:
+      _andi(T, Src0R, 0x1);
+      break;
+    case IceType_i8:
+      _andi(T, Src0R, 0xff);
+      break;
+    case IceType_i16:
+      _andi(T, Src0R, 0xffff);
+      break;
+    default:
+      _mov(T, Src0R);
+      break;
+    }
     _mov(Dest, T);
     break;
   }
   case InstCast::Fptrunc: {
     assert(Dest->getType() == IceType_f32);
     assert(Src0->getType() == IceType_f64);
     auto *DestR = legalizeToReg(Dest);
     auto *Src0R = legalizeToReg(Src0);
     _cvt_s_d(DestR, Src0R);
     _mov(Dest, DestR);
@@ skipping 35 matching lines @@
   }
   case InstCast::Sitofp:
   case InstCast::Uitofp: {
     if (llvm::isa<Variable64On32>(Dest)) {
       llvm::report_fatal_error("i64-to-fp should have been prelowered.");
       return;
     }
     if (Src0Ty != IceType_i64) {
       Variable *Src0R = legalizeToReg(Src0);
       auto *T0R = Src0R;
-      if (Src0Ty != IceType_i32 && CastKind == InstCast::Uitofp) {
+      if (Src0Ty != IceType_i32) {
         T0R = makeReg(IceType_i32);
-        lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
+        if (CastKind == InstCast::Uitofp)
+          lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
+        else
+          lowerCast(InstCast::create(Func, InstCast::Sext, T0R, Src0R));
       }
       if (isScalarIntegerType(Src0Ty) && DestTy == IceType_f32) {
         Variable *FTmp1 = makeReg(IceType_f32);
         Variable *FTmp2 = makeReg(IceType_f32);
         _mtc1(FTmp1, T0R);
         _cvt_s_w(FTmp2, FTmp1);
         _mov(Dest, FTmp2);
         return;
       }
       if (isScalarIntegerType(Src0Ty) && DestTy == IceType_f64) {
@@ skipping 41 matching lines @@
     case IceType_f32: {
       Variable *Src0R = legalizeToReg(Src0);
       _mov(Dest, Src0R);
       break;
     }
     case IceType_i64: {
       assert(Src0->getType() == IceType_f64);
       Variable *Src0R = legalizeToReg(Src0);
       auto *T = llvm::cast<Variable64On32>(Func->makeVariable(IceType_i64));
       T->initHiLo(Func);
-      T->getHi()->setMustHaveReg();
-      T->getLo()->setMustHaveReg();
-      _mov(T, Src0R);
+      T->getHi()->setMustNotHaveReg();
+      T->getLo()->setMustNotHaveReg();
+      Context.insert<InstFakeDef>(T->getHi());
+      Context.insert<InstFakeDef>(T->getLo());
+      _mov_fp64_to_i64(T->getHi(), Src0R, Int64_Hi);
+      _mov_fp64_to_i64(T->getLo(), Src0R, Int64_Lo);
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_f64: {
       assert(Src0->getType() == IceType_i64);
       const uint32_t Mask = 0xFFFFFFFF;
       if (auto *C64 = llvm::dyn_cast<ConstantInteger64>(Src0)) {
         Variable *RegHi, *RegLo;
         const uint64_t Value = C64->getValue();
         uint64_t Upper32Bits = (Value >> INT32_BITS) & Mask;
@@ skipping 551 matching lines @@
     auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest);
     VDest->initVecElement(Func);
     // Temp vector variable
     auto *TDest = makeReg(DestTy);
     auto *TVDest = llvm::dyn_cast<VariableVecOn32>(TDest);
     TVDest->initVecElement(Func);
     // Destination element
     auto *DstE = TVDest->getContainers()[Index / ElemPerCont];
     // Element to insert
     auto *Src1R = legalizeToReg(Instr->getSrc(1));
-    auto *TReg1 = makeReg(Src1R->getType());
-    auto *TReg2 = makeReg(Src1R->getType());
-    auto *TReg3 = makeReg(Src1R->getType());
-    auto *TReg4 = makeReg(Src1R->getType());
-    auto *TReg5 = makeReg(Src1R->getType());
-    auto *TDReg = makeReg(Src1R->getType());
+    auto *TReg1 = makeReg(IceType_i32);
+    auto *TReg2 = makeReg(IceType_i32);
+    auto *TReg3 = makeReg(IceType_i32);
+    auto *TReg4 = makeReg(IceType_i32);
+    auto *TReg5 = makeReg(IceType_i32);
+    auto *TDReg = makeReg(IceType_i32);
     // Position of the element in the container
     uint32_t PosInCont = Index % ElemPerCont;
     // Load source vector in a temporary vector
     for (SizeT i = 0; i < TVDest->ContainersPerVector; ++i) {
       auto *DCont = TVDest->getContainers()[i];
       // Do not define DstE as we are going to redefine it
       if (DCont == DstE)
         continue;
       auto *SCont = Src0R->getContainers()[i];
       auto *TReg = makeReg(IceType_i32);
@@ skipping 44 matching lines @@
       case 2:
         _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source
         _sll(TReg5, TReg1, 16);    // Position in the destination
         _lui(TReg2, Ctx->getConstantInt32(0xff00));
         _ori(TReg3, TReg2, 0xffff);
         _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element
         _or(TDReg, TReg5, TReg4);
         _mov(DstE, TDReg);
         break;
       case 3:
-        _srl(TReg1, Src1R, 24); // Position in the destination
+        _sll(TReg1, Src1R, 24); // Position in the destination
         _sll(TReg2, SrcE, 8);
         _srl(TReg3, TReg2, 8); // Clear bits[31:24] of element
         _or(TDReg, TReg1, TReg3);
         _mov(DstE, TDReg);
         break;
       default:
         llvm::report_fatal_error("InsertElement: Invalid PosInCont");
         break;
       }
     }
@@ skipping 1460 matching lines @@
       // Use addiu if the immediate is a 16bit value. Otherwise load it
       // using a lui-ori instructions.
       Variable *Reg = makeReg(Ty, RegNum);
       if (isInt<16>(int32_t(Value))) {
         Variable *Zero = makeReg(Ty, RegMIPS32::Reg_ZERO);
         Context.insert<InstFakeDef>(Zero);
         _addiu(Reg, Zero, Value);
       } else {
         uint32_t UpperBits = (Value >> 16) & 0xFFFF;
         uint32_t LowerBits = Value & 0xFFFF;
-        Variable *TReg = makeReg(Ty, RegNum);
         if (LowerBits) {
+          Variable *TReg = makeReg(Ty, RegNum);
           _lui(TReg, Ctx->getConstantInt32(UpperBits));
           _ori(Reg, TReg, LowerBits);
         } else {
           _lui(Reg, Ctx->getConstantInt32(UpperBits));
         }
       }
       return Reg;
     } else if (isScalarFloatingType(Ty)) {
       auto *CFrom = llvm::cast<Constant>(From);
       Variable *TReg = makeReg(Ty);
@@ skipping 232 matching lines @@
     if (auto *CallTargetR = llvm::dyn_cast<Variable>(CallTarget)) {
       Variable *T6 = Target->getPhysicalRegister(RegMIPS32::Reg_T6);
       Target->_and(CallTargetR, CallTargetR, T6);
     }
   }
   return Target->Context.insert<InstMIPS32Call>(ReturnReg, CallTarget);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice