PPC: Implement VSX instructions

src/ppc/constants-ppc.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_PPC_CONSTANTS_PPC_H_
 #define V8_PPC_CONSTANTS_PPC_H_
 
 #include <stdint.h>
 
 #include "src/base/logging.h"
@@ skipping 127 matching lines @@
   LFS = 48 << 26,      // Load Floating-Point Single
   LFSU = 49 << 26,     // Load Floating-Point Single with Update
   LFD = 50 << 26,      // Load Floating-Point Double
   LFDU = 51 << 26,     // Load Floating-Point Double with Update
   STFS = 52 << 26,     // Store Floating-Point Single
   STFSU = 53 << 26,    // Store Floating-Point Single with Update
   STFD = 54 << 26,     // Store Floating-Point Double
   STFDU = 55 << 26,    // Store Floating-Point Double with Update
   LD = 58 << 26,       // Load Double Word
   EXT3 = 59 << 26,     // Extended code set 3
+  EXT6 = 60 << 26,     // Extended code set 6
   STD = 62 << 26,      // Store Double Word (optionally with Update)
   EXT4 = 63 << 26      // Extended code set 4
 };
 
 // Bits 10-1
 enum OpcodeExt1 {
   MCRF = 0 << 1,      // Move Condition Register Field
   BCLRX = 16 << 1,    // Branch Conditional Link Register
   CRNOR = 33 << 1,    // Condition Register NOR)
   RFI = 50 << 1,      // Return from Interrupt
@@ skipping 149 matching lines @@
   // Bits 4-2
   RLDICL = 0 << 1,  // Rotate Left Double Word Immediate then Clear Left
   RLDICR = 2 << 1,  // Rotate Left Double Word Immediate then Clear Right
   RLDIC = 4 << 1,   // Rotate Left Double Word Immediate then Clear
   RLDIMI = 6 << 1,  // Rotate Left Double Word Immediate then Mask Insert
   // Bits 4-1
   RLDCL = 8 << 1,  // Rotate Left Double Word then Clear Left
   RLDCR = 9 << 1   // Rotate Left Double Word then Clear Right
 };
 
+// Bits 10-3
+#define XX3_OPCODE_LIST(V)                                   \
+  V(xsaddsp, XSADDSP, 0 << 3)   /* VSX Scalar Add SP */      \
+  V(xssubsp, XSSUBSP, 8 << 3)   /* VSX Scalar Subtract SP */ \
+  V(xsmulsp, XSMULSP, 16 << 3)  /* VSX Scalar Multiply SP */ \
+  V(xsdivsp, XSDIVSP, 24 << 3)  /* VSX Scalar Divide SP */   \
+  V(xsadddp, XSADDDP, 32 << 3)  /* VSX Scalar Add DP */      \
+  V(xssubdp, XSSUBDP, 40 << 3)  /* VSX Scalar Subtract DP */ \
+  V(xsmuldp, XSMULDP, 48 << 3)  /* VSX Scalar Multiply DP */ \
+  V(xsdivdp, XSDIVDP, 56 << 3)  /* VSX Scalar Divide DP */   \
+  V(xsmaxdp, XSMAXDP, 160 << 3) /* VSX Scalar Maximum DP */  \
+  V(xsmindp, XSMINDP, 168 << 3) /* VSX Scalar Minimum DP */
+
+// Bits 10-2
+#define XX2_OPCODE_LIST(V)                                          \
+  V(XSCVDPSP, XSCVDPSP, 265 << 2) /* VSX Scalar Convert DP to SP */ \
+  V(XSCVSPDP, XSCVSPDP, 329 << 2) /* VSX Scalar Convert SP to DP */
+
+enum OpcodeExt6 {
+#define DECLARE_OPCODES(name, opcode_name, opcode_value) \
+  opcode_name = opcode_value,
+  XX3_OPCODE_LIST(DECLARE_OPCODES) XX2_OPCODE_LIST(DECLARE_OPCODES)
+#undef DECLARE_OPCODES
+};
+
 // Instruction encoding bits and masks.
 enum {
   // Instruction encoding bit
   B1 = 1 << 1,
+  B2 = 1 << 2,
+  B3 = 1 << 3,
   B4 = 1 << 4,
   B5 = 1 << 5,
   B7 = 1 << 7,
   B8 = 1 << 8,
   B9 = 1 << 9,
   B12 = 1 << 12,
   B18 = 1 << 18,
   B19 = 1 << 19,
   B20 = 1 << 20,
   B22 = 1 << 22,
@@ skipping 262 matching lines @@
   // Lookup the register number for the name provided.
   static int Number(const char* name);
 
  private:
   static const char* names_[kNumDoubleRegisters];
 };
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_PPC_CONSTANTS_PPC_H_