Begins work on arm64 floating point instructions.

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 125 matching lines @@
 
 
 // C++ ABI call registers.
 const RegList kAbiArgumentCpuRegs =
     (1 << R0) | (1 << R1) | (1 << R2) | (1 << R3) |
     (1 << R4) | (1 << R5) | (1 << R6) | (1 << R7);
 const RegList kAbiPreservedCpuRegs =
     (1 << R19) | (1 << R20) | (1 << R21) | (1 << R22) |
     (1 << R23) | (1 << R24) | (1 << R25) | (1 << R26) |
     (1 << R27) | (1 << R28);
+const Register kAbiFirstPreservedCpuReg = R19;
+const Register kAbiLastPreservedCpuReg = R28;
 const int kAbiPreservedCpuRegCount = 10;
 const VRegister kAbiFirstPreservedFpuReg = V8;
 const VRegister kAbiLastPreservedFpuReg = V15;
 const int kAbiPreservedFpuRegCount = 8;
 
 // CPU registers available to Dart allocator.
 const RegList kDartAvailableCpuRegs =
     (1 << R0)  | (1 << R1)  | (1 << R2)  | (1 << R3)  |
     (1 << R4)  | (1 << R5)  | (1 << R6)  | (1 << R7)  |
     (1 << R8)  | (1 << R9)  | (1 << R10) | (1 << R11) |
@@ skipping 96 matching lines @@
   LoadStoreFixed = B27,
 
   DPRegisterMask = 0x0e000000,
   DPRegisterFixed = B27 | B25,
 
   DPSimd1Mask = 0x1e000000,
   DPSimd1Fixed = B27 | B26 | B25,
 
   DPSimd2Mask = 0x1e000000,
   DPSimd2Fixed = B28 | DPSimd1Fixed,
+
+  FPMask = 0x5e000000,
+  FPFixed = B28 | B27 | B26 | B25,
 };
 
 // C3.2.1
 enum CompareAndBranchOp {
   CompareAndBranchMask = 0x7e000000,
   CompareAndBranchFixed = CompareBranchFixed | B29,
   CBZ = CompareBranchFixed,
   CBNZ = CompareBranchFixed | B24,
 };
 
@@ skipping 134 matching lines @@
   AND = LogicalShiftFixed,
   BIC = LogicalShiftFixed | B21,
   ORR = LogicalShiftFixed | B29,
   ORN = LogicalShiftFixed | B29 | B21,
   EOR = LogicalShiftFixed | B30,
   EON = LogicalShiftFixed | B30 | B21,
   ANDS = LogicalShiftFixed | B30 | B29,
   BICS = LogicalShiftFixed | B30 | B29 | B21,
 };
 
+// C3.6.28
+enum FPImmOp {
+  FPImmMask = 0x5f201c00,
+  FPImmFixed = FPFixed | B21 | B12,
+  FMOVSI = FPImmFixed,
+  FMOVDI = FPImmFixed | B22,
+};
+
+// C3.6.29
+enum FPIntCvtOp {
+  FPIntCvtMask = 0x5f20fc00,
+  FPIntCvtFixed = FPFixed | B21,
+  FMOVRD = FPIntCvtFixed | B31 | B22 | B18 | B17,
+  FMOVDR = FPIntCvtFixed | B31 | B22 | B18 | B17 | B16,
+};
+
+
 #define APPLY_OP_LIST(_V)                                                      \
 _V(DPImmediate)                                                                \
 _V(CompareBranch)                                                              \
 _V(LoadStore)                                                                  \
 _V(DPRegister)                                                                 \
 _V(DPSimd1)                                                                    \
 _V(DPSimd2)                                                                    \
+_V(FP)                                                                         \
 _V(CompareAndBranch)                                                           \
 _V(ConditionalBranch)                                                          \
 _V(ExceptionGen)                                                               \
 _V(System)                                                                     \
 _V(TestAndBranch)                                                              \
 _V(UnconditionalBranch)                                                        \
 _V(UnconditionalBranchReg)                                                     \
 _V(LoadStoreReg)                                                               \
 _V(LoadRegLiteral)                                                             \
 _V(AddSubImm)                                                                  \
 _V(LogicalImm)                                                                 \
 _V(MoveWide)                                                                   \
 _V(PCRel)                                                                      \
 _V(AddSubShiftExt)                                                             \
 _V(ConditionalSelect)                                                          \
 _V(MiscDP2Source)                                                              \
 _V(MiscDP3Source)                                                              \
 _V(LogicalShift)                                                               \
+_V(FPImm)                                                                      \
+_V(FPIntCvt)                                                                   \
 
 
 enum Shift {
   kNoShift = -1,
   LSL = 0,  // Logical shift left
   LSR = 1,  // Logical shift right
   ASR = 2,  // Arithmetic shift right
   ROR = 3,  // Rotate right
   kMaxShift = 4,
 };
@@ skipping 36 matching lines @@
   kRdBits = 5,
   kRnShift = 5,
   kRnBits = 5,
   kRaShift = 10,
   kRaBits = 5,
   kRmShift = 16,
   kRmBits = 5,
   kRtShift = 0,
   kRtBits = 5,
 
+  // V Registers.
+  kVdShift = 0,
+  kVdBits = 5,
+  kVnShift = 5,
+  kVnBits = 5,
+
   // Immediates.
   kImm3Shift = 10,
   kImm3Bits = 3,
   kImm6Shift = 10,
   kImm6Bits = 6,
+  kImm8Shift = 13,
+  kImm8Bits = 8,
   kImm9Shift = 12,
   kImm9Bits = 9,
   kImm12Shift = 10,
   kImm12Bits = 12,
   kImm12ShiftShift = 22,
   kImm12ShiftBits = 2,
   kImm14Shift = 5,
   kImm14Bits = 14,
   kImm16Shift = 5,
   kImm16Bits = 16,
@@ skipping 136 matching lines @@
                                         Bits(kRdShift, kRdBits)); }
   inline Register RnField() const { return static_cast<Register>(
                                         Bits(kRnShift, kRnBits)); }
   inline Register RaField() const { return static_cast<Register>(
                                         Bits(kRaShift, kRaBits)); }
   inline Register RmField() const { return static_cast<Register>(
                                         Bits(kRmShift, kRmBits)); }
   inline Register RtField() const { return static_cast<Register>(
                                         Bits(kRtShift, kRtBits)); }
 
+  inline VRegister VdField() const { return static_cast<VRegister>(
+                                        Bits(kVdShift, kVdBits)); }
+  inline VRegister VnField() const { return static_cast<VRegister>(
+                                        Bits(kVnShift, kVnBits)); }
+
   // Immediates
   inline int Imm3Field() const { return Bits(kImm3Shift, kImm3Bits); }
   inline int Imm6Field() const { return Bits(kImm6Shift, kImm6Bits); }
-
+  inline int Imm8Field() const { return Bits(kImm8Shift, kImm8Bits); }
   inline int Imm9Field() const { return Bits(kImm9Shift, kImm9Bits); }
   // Sign-extended Imm9Field()
   inline int64_t SImm9Field() const {
       return (static_cast<int32_t>(Imm9Field()) << 23) >> 23; }
 
   inline int Imm12Field() const { return Bits(kImm12Shift, kImm12Bits); }
   inline int Imm12ShiftField() const {
     return Bits(kImm12ShiftShift, kImm12ShiftBits); }
 
   inline int Imm16Field() const { return Bits(kImm16Shift, kImm16Bits); }
@@ skipping 123 matching lines @@
           return RepeatBitsAcrossReg(reg_size,
                                      RotateRight(bits, imm_r & mask, width),
                                      width);
         }
       }
     }
     UNREACHABLE();
     return 0;
   }
 
+  static int64_t VFPExpandImm(uint8_t imm8) {
+    const int64_t sign =
+        static_cast<int64_t>((imm8 & 0x80) >> 7) << 63;
+    const int64_t hi_exp =
+        static_cast<int64_t>(!((imm8 & 0x40) >> 6)) << 62;
+    const int64_t mid_exp =
+        (((imm8 & 0x40) >> 6) == 0) ? 0 : (0xffLL << 54);
+    const int64_t low_exp =
+        static_cast<int64_t>((imm8 & 0x30) >> 4) << 52;
+    const int64_t frac =
+        static_cast<int64_t>(imm8 & 0x0f) << 48;
+    return sign | hi_exp | mid_exp | low_exp | frac;
+  }
+
   // Instructions are read out of a code stream. The only way to get a
   // reference to an instruction is to convert a pointer. There is no way
   // to allocate or create instances of class Instr.
   // Use the At(pc) function to create references to Instr.
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_