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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> // For assert | 5 #include <assert.h> // For assert |
6 #include <limits.h> // For LONG_MIN, LONG_MAX. | 6 #include <limits.h> // For LONG_MIN, LONG_MAX. |
7 | 7 |
8 #if V8_TARGET_ARCH_S390 | 8 #if V8_TARGET_ARCH_S390 |
9 | 9 |
10 #include "src/base/bits.h" | 10 #include "src/base/bits.h" |
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3335 } | 3335 } |
3336 #else | 3336 #else |
3337 if (is_int20(opnd.offset())) { | 3337 if (is_int20(opnd.offset())) { |
3338 msg(dst, opnd); | 3338 msg(dst, opnd); |
3339 } else { | 3339 } else { |
3340 UNIMPLEMENTED(); | 3340 UNIMPLEMENTED(); |
3341 } | 3341 } |
3342 #endif | 3342 #endif |
3343 } | 3343 } |
3344 | 3344 |
| 3345 void MacroAssembler::Sqrt(DoubleRegister result, DoubleRegister input) { |
| 3346 sqdbr(result, input); |
| 3347 } |
| 3348 void MacroAssembler::Sqrt(DoubleRegister result, const MemOperand& input) { |
| 3349 if (is_uint12(input.offset())) { |
| 3350 sqdb(result, input); |
| 3351 } else { |
| 3352 ldy(result, input); |
| 3353 sqdbr(result, result); |
| 3354 } |
| 3355 } |
3345 //---------------------------------------------------------------------------- | 3356 //---------------------------------------------------------------------------- |
3346 // Add Instructions | 3357 // Add Instructions |
3347 //---------------------------------------------------------------------------- | 3358 //---------------------------------------------------------------------------- |
3348 | 3359 |
3349 // Add 32-bit (Register dst = Register dst + Immediate opnd) | 3360 // Add 32-bit (Register dst = Register dst + Immediate opnd) |
3350 void MacroAssembler::Add32(Register dst, const Operand& opnd) { | 3361 void MacroAssembler::Add32(Register dst, const Operand& opnd) { |
3351 if (is_int16(opnd.immediate())) | 3362 if (is_int16(opnd.immediate())) |
3352 ahi(dst, opnd); | 3363 ahi(dst, opnd); |
3353 else | 3364 else |
3354 afi(dst, opnd); | 3365 afi(dst, opnd); |
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5130 } | 5141 } |
5131 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); | 5142 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); |
5132 ExtractBit(r0, dividend, 31); | 5143 ExtractBit(r0, dividend, 31); |
5133 AddP(result, r0); | 5144 AddP(result, r0); |
5134 } | 5145 } |
5135 | 5146 |
5136 } // namespace internal | 5147 } // namespace internal |
5137 } // namespace v8 | 5148 } // namespace v8 |
5138 | 5149 |
5139 #endif // V8_TARGET_ARCH_S390 | 5150 #endif // V8_TARGET_ARCH_S390 |
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