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Side by Side Diff: base/cpu.cc

Issue 2611683002: Set ecx to 0 when calling cpuid. (Closed)
Patch Set: Created 3 years, 11 months ago
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1 // Copyright (c) 2012 The Chromium Authors. All rights reserved. 1 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "base/cpu.h" 5 #include "base/cpu.h"
6 6
7 #include <limits.h> 7 #include <limits.h>
8 #include <stddef.h> 8 #include <stddef.h>
9 #include <stdint.h> 9 #include <stdint.h>
10 #include <string.h> 10 #include <string.h>
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53 } 53 }
54 54
55 namespace { 55 namespace {
56 56
57 #if defined(ARCH_CPU_X86_FAMILY) 57 #if defined(ARCH_CPU_X86_FAMILY)
58 #ifndef _MSC_VER 58 #ifndef _MSC_VER
59 59
60 #if defined(__pic__) && defined(__i386__) 60 #if defined(__pic__) && defined(__i386__)
61 61
62 void __cpuid(int cpu_info[4], int info_type) { 62 void __cpuid(int cpu_info[4], int info_type) {
63 __asm__ volatile ( 63 __asm__ volatile(
64 "mov %%ebx, %%edi\n" 64 "mov %%ebx, %%edi\n"
65 "cpuid\n" 65 "cpuid\n"
66 "xchg %%edi, %%ebx\n" 66 "xchg %%edi, %%ebx\n"
67 : "=a"(cpu_info[0]), "=D"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3]) 67 : "=a"(cpu_info[0]), "=D"(cpu_info[1]), "=c"(cpu_info[2]),
68 : "a"(info_type) 68 "=d"(cpu_info[3])
69 ); 69 : "a"(info_type), "c"(0));
70 } 70 }
71 71
72 #else 72 #else
73 73
74 void __cpuid(int cpu_info[4], int info_type) { 74 void __cpuid(int cpu_info[4], int info_type) {
75 __asm__ volatile ( 75 __asm__ volatile("cpuid\n"
76 "cpuid\n" 76 : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]),
77 : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3]) 77 "=d"(cpu_info[3])
78 : "a"(info_type) 78 : "a"(info_type), "c"(0));
79 );
80 } 79 }
81 80
82 #endif 81 #endif
83 82
84 // _xgetbv returns the value of an Intel Extended Control Register (XCR). 83 // _xgetbv returns the value of an Intel Extended Control Register (XCR).
85 // Currently only XCR0 is defined by Intel so |xcr| should always be zero. 84 // Currently only XCR0 is defined by Intel so |xcr| should always be zero.
86 uint64_t _xgetbv(uint32_t xcr) { 85 uint64_t _xgetbv(uint32_t xcr) {
87 uint32_t eax, edx; 86 uint32_t eax, edx;
88 87
89 __asm__ volatile ( 88 __asm__ volatile (
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232 if (has_sse42()) return SSE42; 231 if (has_sse42()) return SSE42;
233 if (has_sse41()) return SSE41; 232 if (has_sse41()) return SSE41;
234 if (has_ssse3()) return SSSE3; 233 if (has_ssse3()) return SSSE3;
235 if (has_sse3()) return SSE3; 234 if (has_sse3()) return SSE3;
236 if (has_sse2()) return SSE2; 235 if (has_sse2()) return SSE2;
237 if (has_sse()) return SSE; 236 if (has_sse()) return SSE;
238 return PENTIUM; 237 return PENTIUM;
239 } 238 }
240 239
241 } // namespace base 240 } // namespace base
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