MIPS[64]: Add support for FPR content in simulator trace.

src/mips64/simulator-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_MIPS64
@@ skipping 1608 matching lines @@
 // TODO(plind): refactor this messy debug code when we do unaligned access.
 void Simulator::DieOrDebug() {
   if (1) {  // Flag for this was removed.
     MipsDebugger dbg(this);
     dbg.Debug();
   } else {
     base::OS::Abort();
   }
 }
 
+void Simulator::TraceRegWr(int64_t value, TraceType t) {
+  if (::v8::internal::FLAG_trace_sim) {
+    union {
+      int64_t fmt_int64;
+      int32_t fmt_int32[2];
+      float fmt_float[2];
+      double fmt_double;
+    } v;
+    v.fmt_int64 = value;
 
-void Simulator::TraceRegWr(int64_t value) {
-  if (::v8::internal::FLAG_trace_sim) {
-    SNPrintF(trace_buf_, "%016" PRIx64 " ", value);
+    switch (t) {
+      case WORD:
+        SNPrintF(trace_buf_, "%016" PRIx64 "    (%" PRId64 ")    int32:%" PRId32
+                             " uint32:%" PRIu32,
+                 v.fmt_int64, icount_, v.fmt_int32[0], v.fmt_int32[0]);
+        break;
+      case DWORD:
+        SNPrintF(trace_buf_, "%016" PRIx64 "    (%" PRId64 ")    int64:%" PRId64
+                             " uint64:%" PRIu64,
+                 value, icount_, value, value);
+        break;
+      case FLOAT:
+        SNPrintF(trace_buf_, "%016" PRIx64 "    (%" PRId64 ")    flt:%e",
+                 v.fmt_int64, icount_, v.fmt_float[0]);
+        break;
+      case DOUBLE:
+        SNPrintF(trace_buf_, "%016" PRIx64 "    (%" PRId64 ")    dbl:%e",
+                 v.fmt_int64, icount_, v.fmt_double);
+        break;
+      case FLOAT_DOUBLE:
+        SNPrintF(trace_buf_, "%016" PRIx64 "    (%" PRId64 ")    flt:%e dbl:%e",
+                 v.fmt_int64, icount_, v.fmt_float[0], v.fmt_double);
+        break;
+      case WORD_DWORD:
+        SNPrintF(trace_buf_,
+                 "%016" PRIx64 "    (%" PRId64 ")    int32:%" PRId32
+                 " uint32:%" PRIu32 " int64:%" PRId64 " uint64:%" PRIu64,
+                 v.fmt_int64, icount_, v.fmt_int32[0], v.fmt_int32[0],
+                 v.fmt_int64, v.fmt_int64);
+        break;
+      default:

[ivica.bogosavljevic, 2017/01/23 13:22:38]

Everything mentioned in simulator-mips.cc applies here as well

[Ilija.Pavlovic1, 2017/01/27 09:10:12]

Done.

+        break;
+    }
   }
 }
 
+// TODO(plind): consider making icount_ printing a flag option.
+void Simulator::TraceMemRd(int64_t addr, int64_t value, TraceType t) {
+  if (::v8::internal::FLAG_trace_sim) {
+    union {
+      int64_t fmt_int64;
+      int32_t fmt_int32[2];
+      float fmt_float[2];
+      double fmt_double;
+    } v;
+    v.fmt_int64 = value;
 
-// TODO(plind): consider making icount_ printing a flag option.
-void Simulator::TraceMemRd(int64_t addr, int64_t value) {
-  if (::v8::internal::FLAG_trace_sim) {
-    SNPrintF(trace_buf_,
-             "%016" PRIx64 "  <-- [%016" PRIx64 " ]    (%" PRId64 " )", value,
-             addr, icount_);
+    switch (t) {
+      case WORD:
+        SNPrintF(trace_buf_,
+                 "%016" PRIx64 "  <-- [%016" PRIx64 " ]    (%" PRId64
+                 ")    int32:%" PRId32 " uint32:%" PRIu32,
+                 v.fmt_int64, addr, icount_, v.fmt_int32[0], v.fmt_int32[0]);
+        break;
+      case DWORD:
+        SNPrintF(trace_buf_,
+                 "%016" PRIx64 "  <-- [%016" PRIx64 " ]    (%" PRId64
+                 ")    int64:%" PRId64 " uint64:%" PRIu64,
+                 value, addr, icount_, value, value);
+        break;
+      case FLOAT:
+        SNPrintF(trace_buf_, "%016" PRIx64 "  <-- [%016" PRIx64
+                             " ]    (%" PRId64 ")    flt:%e",
+                 v.fmt_int64, addr, icount_, v.fmt_float[0]);
+        break;
+      case DOUBLE:
+        SNPrintF(trace_buf_, "%016" PRIx64 "  <-- [%016" PRIx64
+                             " ]    (%" PRId64 ")    dbl:%e",
+                 v.fmt_int64, addr, icount_, v.fmt_double);
+        break;
+      case FLOAT_DOUBLE:
+        SNPrintF(trace_buf_, "%016" PRIx64 "  <-- [%016" PRIx64
+                             " ]    (%" PRId64 ")    flt:%e dbl:%e",
+                 v.fmt_int64, addr, icount_, v.fmt_float[0], v.fmt_double);
+        break;
+      default:
+        break;
+    }
   }
 }
 
 
 void Simulator::TraceMemWr(int64_t addr, int64_t value, TraceType t) {
   if (::v8::internal::FLAG_trace_sim) {
     switch (t) {
       case BYTE:
-        SNPrintF(trace_buf_, "               %02x --> [%016" PRIx64 " ]",
-                 static_cast<int8_t>(value), addr);
+        SNPrintF(trace_buf_, "               %02" PRIx8 " --> [%016" PRIx64
+                             " ]    (%" PRId64 ")",
+                 static_cast<uint8_t>(value), addr, icount_);
         break;
       case HALF:
-        SNPrintF(trace_buf_, "            %04x --> [%016" PRIx64 " ]",
-                 static_cast<int16_t>(value), addr);
+        SNPrintF(trace_buf_, "            %04" PRIx16 " --> [%016" PRIx64
+                             " ]    (%" PRId64 ")",
+                 static_cast<uint16_t>(value), addr, icount_);
         break;
       case WORD:
-        SNPrintF(trace_buf_, "        %08x --> [%016" PRIx64 " ]",
-                 static_cast<int32_t>(value), addr);
+        SNPrintF(trace_buf_,
+                 "        %08" PRIx32 " --> [%016" PRIx64 " ]    (%" PRId64 ")",
+                 static_cast<uint32_t>(value), addr, icount_);
         break;
       case DWORD:
         SNPrintF(trace_buf_,
                  "%016" PRIx64 "  --> [%016" PRIx64 " ]    (%" PRId64 " )",
                  value, addr, icount_);
         break;
+      default:
+        break;
     }
   }
 }
 
 
 // TODO(plind): sign-extend and zero-extend not implmented properly
 // on all the ReadXX functions, I don't think re-interpret cast does it.
-int32_t Simulator::ReadW(int64_t addr, Instruction* instr) {
+int32_t Simulator::ReadW(int64_t addr, Instruction* instr, TraceType t) {
   if (addr >=0 && addr < 0x400) {
     // This has to be a NULL-dereference, drop into debugger.
     PrintF("Memory read from bad address: 0x%08" PRIx64 " , pc=0x%08" PRIxPTR
            " \n",
            addr, reinterpret_cast<intptr_t>(instr));
     DieOrDebug();
   }
   if ((addr & 0x3) == 0 || kArchVariant == kMips64r6) {
     int32_t* ptr = reinterpret_cast<int32_t*>(addr);
-    TraceMemRd(addr, static_cast<int64_t>(*ptr));
+    TraceMemRd(addr, static_cast<int64_t>(*ptr), t);
     return *ptr;
   }
   PrintF("Unaligned read at 0x%08" PRIx64 " , pc=0x%08" V8PRIxPTR "\n", addr,
          reinterpret_cast<intptr_t>(instr));
   DieOrDebug();
   return 0;
 }
 
 
 uint32_t Simulator::ReadWU(int64_t addr, Instruction* instr) {
   if (addr >=0 && addr < 0x400) {
     // This has to be a NULL-dereference, drop into debugger.
     PrintF("Memory read from bad address: 0x%08" PRIx64 " , pc=0x%08" PRIxPTR
            " \n",
            addr, reinterpret_cast<intptr_t>(instr));
     DieOrDebug();
   }
   if ((addr & 0x3) == 0 || kArchVariant == kMips64r6) {
     uint32_t* ptr = reinterpret_cast<uint32_t*>(addr);
-    TraceMemRd(addr, static_cast<int64_t>(*ptr));
+    TraceMemRd(addr, static_cast<int64_t>(*ptr), WORD);
     return *ptr;
   }
   PrintF("Unaligned read at 0x%08" PRIx64 " , pc=0x%08" V8PRIxPTR "\n", addr,
          reinterpret_cast<intptr_t>(instr));
   DieOrDebug();
   return 0;
 }
 
 
 void Simulator::WriteW(int64_t addr, int32_t value, Instruction* instr) {
@@ skipping 737 matching lines @@
           result = upper;
           break;
         case kRoundToMinusInf:
           result = lower;
           break;
       }
       set_fpu_register_float(fd_reg(), result);
       if (result != fs) {
         set_fcsr_bit(kFCSRInexactFlagBit, true);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     }
     case ADD_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float lhs, float rhs) { return lhs + rhs; },
                                  fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case SUB_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float lhs, float rhs) { return lhs - rhs; },
                                  fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case MADDF_S:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), std::fma(fs, ft, fd));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case MSUBF_S:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), std::fma(-fs, ft, fd));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case MUL_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float lhs, float rhs) { return lhs * rhs; },
                                  fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case DIV_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float lhs, float rhs) { return lhs / rhs; },
                                  fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case ABS_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float fs) { return FPAbs(fs); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case MOV_S:
       set_fpu_register_float(fd_reg(), fs);
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case NEG_S:
       set_fpu_register_float(
           fd_reg(), FPUCanonalizeOperation([](float src) { return -src; },
                                            KeepSign::yes, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case SQRT_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float src) { return std::sqrt(src); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case RSQRT_S:
       set_fpu_register_float(
           fd_reg(), FPUCanonalizeOperation(
                         [](float src) { return 1.0 / std::sqrt(src); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case RECIP_S:
       set_fpu_register_float(
           fd_reg(),
           FPUCanonalizeOperation([](float src) { return 1.0 / src; }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case C_F_D:
       set_fcsr_bit(fcsr_cc, false);
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_UN_D:
       set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_EQ_D:
       set_fcsr_bit(fcsr_cc, (fs == ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_UEQ_D:
       set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_OLT_D:
       set_fcsr_bit(fcsr_cc, (fs < ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_ULT_D:
       set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_OLE_D:
       set_fcsr_bit(fcsr_cc, (fs <= ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_ULE_D:
       set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case CVT_D_S:
       set_fpu_register_double(fd_reg(), static_cast<double>(fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case CLASS_S: {  // Mips64r6 instruction
       // Convert float input to uint32_t for easier bit manipulation
       uint32_t classed = bit_cast<uint32_t>(fs);
 
       // Extracting sign, exponent and mantissa from the input float
       uint32_t sign = (classed >> 31) & 1;
       uint32_t exponent = (classed >> 23) & 0x000000ff;
       uint32_t mantissa = classed & 0x007fffff;
       uint32_t result;
@@ skipping 43 matching lines @@
 
       // Calculating result according to description of CLASS.S instruction
       result = (posZero << 9) | (posSubnorm << 8) | (posNorm << 7) |
                (posInf << 6) | (negZero << 5) | (negSubnorm << 4) |
                (negNorm << 3) | (negInf << 2) | (quietNan << 1) | signalingNan;
 
       DCHECK(result != 0);
 
       fResult = bit_cast<float>(result);
       set_fpu_register_float(fd_reg(), fResult);
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
 
       break;
     }
     case CVT_L_S: {
       float rounded;
       int64_t result;
       round64_according_to_fcsr(fs, rounded, result, fs);
       set_fpu_register(fd_reg(), result);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case CVT_W_S: {
       float rounded;
       int32_t result;
       round_according_to_fcsr(fs, rounded, result, fs);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
       break;
     }
     case TRUNC_W_S: {  // Truncate single to word (round towards 0).
       float rounded = trunc(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
     } break;
     case TRUNC_L_S: {  // Mips64r2 instruction.
       float rounded = trunc(fs);
       int64_t result = static_cast<int64_t>(rounded);
       set_fpu_register(fd_reg(), result);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case ROUND_W_S: {
       float rounded = std::floor(fs + 0.5);
       int32_t result = static_cast<int32_t>(rounded);
       if ((result & 1) != 0 && result - fs == 0.5) {
         // If the number is halfway between two integers,
         // round to the even one.
         result--;
       }
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
       break;
     }
     case ROUND_L_S: {  // Mips64r2 instruction.
       float rounded = std::floor(fs + 0.5);
       int64_t result = static_cast<int64_t>(rounded);
       if ((result & 1) != 0 && result - fs == 0.5) {
         // If the number is halfway between two integers,
         // round to the even one.
         result--;
       }
       int64_t i64 = static_cast<int64_t>(result);
       set_fpu_register(fd_reg(), i64);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case FLOOR_L_S: {  // Mips64r2 instruction.
       float rounded = floor(fs);
       int64_t result = static_cast<int64_t>(rounded);
       set_fpu_register(fd_reg(), result);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case FLOOR_W_S:  // Round double to word towards negative infinity.
     {
       float rounded = std::floor(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
     } break;
     case CEIL_W_S:  // Round double to word towards positive infinity.
     {
       float rounded = std::ceil(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
     } break;
     case CEIL_L_S: {  // Mips64r2 instruction.
       float rounded = ceil(fs);
       int64_t result = static_cast<int64_t>(rounded);
       set_fpu_register(fd_reg(), result);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case MINA:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), FPUMinA(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case MAXA:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), FPUMaxA(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case MIN:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), FPUMin(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case MAX:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), FPUMax(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case SEL:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft);
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case SELEQZ_C:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), (ft_int & 0x1) == 0
                                            ? get_fpu_register_float(fs_reg())
                                            : 0.0);
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case SELNEZ_C:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_float(fd_reg(), (ft_int & 0x1) != 0
                                            ? get_fpu_register_float(fs_reg())
                                            : 0.0);
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case MOVZ_C: {
       DCHECK(kArchVariant == kMips64r2);
       if (rt() == 0) {
         set_fpu_register_float(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     }
     case MOVN_C: {
       DCHECK(kArchVariant == kMips64r2);
       if (rt() != 0) {
         set_fpu_register_float(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     }
     case MOVF: {
       // Same function field for MOVT.D and MOVF.D
       uint32_t ft_cc = (ft_reg() >> 2) & 0x7;
       ft_cc = get_fcsr_condition_bit(ft_cc);
 
       if (instr_.Bit(16)) {  // Read Tf bit.
         // MOVT.D
         if (test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg(), fs);
       } else {
         // MOVF.D
         if (!test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     }
     default:
       // TRUNC_W_S ROUND_W_S ROUND_L_S FLOOR_W_S FLOOR_L_S
       // CEIL_W_S CEIL_L_S CVT_PS_S are unimplemented.
       UNREACHABLE();
   }
 }
 
 
@@ skipping 37 matching lines @@
           result = upper;
           break;
         case kRoundToMinusInf:
           result = lower;
           break;
       }
       set_fpu_register_double(fd_reg(), result);
       if (result != fs) {
         set_fcsr_bit(kFCSRInexactFlagBit, true);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case SEL:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SELEQZ_C:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), (ft_int & 0x1) == 0 ? fs : 0.0);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SELNEZ_C:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), (ft_int & 0x1) != 0 ? fs : 0.0);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MOVZ_C: {
       DCHECK(kArchVariant == kMips64r2);
       if (rt() == 0) {
         set_fpu_register_double(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case MOVN_C: {
       DCHECK(kArchVariant == kMips64r2);
       if (rt() != 0) {
         set_fpu_register_double(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case MOVF: {
       // Same function field for MOVT.D and MOVF.D
       uint32_t ft_cc = (ft_reg() >> 2) & 0x7;
       ft_cc = get_fcsr_condition_bit(ft_cc);
       if (instr_.Bit(16)) {  // Read Tf bit.
         // MOVT.D
         if (test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg(), fs);
       } else {
         // MOVF.D
         if (!test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg(), fs);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case MINA:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), FPUMinA(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MAXA:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), FPUMaxA(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MIN:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), FPUMin(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MAX:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), FPUMax(ft, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case ADD_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation(
               [](double lhs, double rhs) { return lhs + rhs; }, fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SUB_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation(
               [](double lhs, double rhs) { return lhs - rhs; }, fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MADDF_D:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), std::fma(fs, ft, fd));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MSUBF_D:
       DCHECK(kArchVariant == kMips64r6);
       set_fpu_register_double(fd_reg(), std::fma(-fs, ft, fd));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MUL_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation(
               [](double lhs, double rhs) { return lhs * rhs; }, fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case DIV_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation(
               [](double lhs, double rhs) { return lhs / rhs; }, fs, ft));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case ABS_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation([](double fs) { return FPAbs(fs); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case MOV_D:
       set_fpu_register_double(fd_reg(), fs);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case NEG_D:
       set_fpu_register_double(
           fd_reg(), FPUCanonalizeOperation([](double src) { return -src; },
                                            KeepSign::yes, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case SQRT_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation([](double fs) { return std::sqrt(fs); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case RSQRT_D:
       set_fpu_register_double(
           fd_reg(), FPUCanonalizeOperation(
                         [](double fs) { return 1.0 / std::sqrt(fs); }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case RECIP_D:
       set_fpu_register_double(
           fd_reg(),
           FPUCanonalizeOperation([](double fs) { return 1.0 / fs; }, fs));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case C_UN_D:
       set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_EQ_D:
       set_fcsr_bit(fcsr_cc, (fs == ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_UEQ_D:
       set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_OLT_D:
       set_fcsr_bit(fcsr_cc, (fs < ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_ULT_D:
       set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_OLE_D:
       set_fcsr_bit(fcsr_cc, (fs <= ft));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case C_ULE_D:
       set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft)));
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     case CVT_W_D: {  // Convert double to word.
       double rounded;
       int32_t result;
       round_according_to_fcsr(fs, rounded, result, fs);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_word_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
       break;
     }
     case ROUND_W_D:  // Round double to word (round half to even).
     {
       double rounded = std::floor(fs + 0.5);
       int32_t result = static_cast<int32_t>(rounded);
       if ((result & 1) != 0 && result - fs == 0.5) {
         // If the number is halfway between two integers,
         // round to the even one.
         result--;
       }
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
     } break;
     case TRUNC_W_D:  // Truncate double to word (round towards 0).
     {
       double rounded = trunc(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
     } break;
     case FLOOR_W_D:  // Round double to word towards negative infinity.
     {
       double rounded = std::floor(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()), WORD);
     } break;
     case CEIL_W_D:  // Round double to word towards positive infinity.
     {
       double rounded = std::ceil(fs);
       int32_t result = static_cast<int32_t>(rounded);
       set_fpu_register_word(fd_reg(), result);
       if (set_fcsr_round_error(fs, rounded)) {
         set_fpu_register_invalid_result(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
     } break;
     case CVT_S_D:  // Convert double to float (single).
       set_fpu_register_float(fd_reg(), static_cast<float>(fs));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case CVT_L_D: {  // Mips64r2: Truncate double to 64-bit long-word.
       double rounded;
       int64_t result;
       round64_according_to_fcsr(fs, rounded, result, fs);
       set_fpu_register(fd_reg(), result);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case ROUND_L_D: {  // Mips64r2 instruction.
       double rounded = std::floor(fs + 0.5);
       int64_t result = static_cast<int64_t>(rounded);
       if ((result & 1) != 0 && result - fs == 0.5) {
         // If the number is halfway between two integers,
         // round to the even one.
         result--;
       }
       int64_t i64 = static_cast<int64_t>(result);
       set_fpu_register(fd_reg(), i64);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case TRUNC_L_D: {  // Mips64r2 instruction.
       double rounded = trunc(fs);
       int64_t result = static_cast<int64_t>(rounded);
       set_fpu_register(fd_reg(), result);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case FLOOR_L_D: {  // Mips64r2 instruction.
       double rounded = floor(fs);
       int64_t result = static_cast<int64_t>(rounded);
       set_fpu_register(fd_reg(), result);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case CEIL_L_D: {  // Mips64r2 instruction.
       double rounded = ceil(fs);
       int64_t result = static_cast<int64_t>(rounded);
       set_fpu_register(fd_reg(), result);
       if (set_fcsr_round64_error(fs, rounded)) {
         set_fpu_register_invalid_result64(fs, rounded);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     }
     case CLASS_D: {  // Mips64r6 instruction
       // Convert double input to uint64_t for easier bit manipulation
       uint64_t classed = bit_cast<uint64_t>(fs);
 
       // Extracting sign, exponent and mantissa from the input double
       uint32_t sign = (classed >> 63) & 1;
       uint32_t exponent = (classed >> 52) & 0x00000000000007ff;
       uint64_t mantissa = classed & 0x000fffffffffffff;
@@ skipping 44 matching lines @@
 
       // Calculating result according to description of CLASS.D instruction
       result = (posZero << 9) | (posSubnorm << 8) | (posNorm << 7) |
                (posInf << 6) | (negZero << 5) | (negSubnorm << 4) |
                (negNorm << 3) | (negInf << 2) | (quietNan << 1) | signalingNan;
 
       DCHECK(result != 0);
 
       dResult = bit_cast<double>(result);
       set_fpu_register_double(fd_reg(), dResult);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
 
       break;
     }
     case C_F_D: {
       set_fcsr_bit(fcsr_cc, false);
+      TraceRegWr(test_fcsr_bit(fcsr_cc));
       break;
     }
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterWRsType() {
   float fs = get_fpu_register_float(fs_reg());
   float ft = get_fpu_register_float(ft_reg());
   int64_t alu_out = 0x12345678;
   switch (instr_.FunctionFieldRaw()) {
     case CVT_S_W:  // Convert word to float (single).
       alu_out = get_fpu_register_signed_word(fs_reg());
       set_fpu_register_float(fd_reg(), static_cast<float>(alu_out));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case CVT_D_W:  // Convert word to double.
       alu_out = get_fpu_register_signed_word(fs_reg());
       set_fpu_register_double(fd_reg(), static_cast<double>(alu_out));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case CMP_AF:
       set_fpu_register_word(fd_reg(), 0);
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UN:
       if (std::isnan(fs) || std::isnan(ft)) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_EQ:
       if (fs == ft) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UEQ:
       if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_LT:
       if (fs < ft) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_ULT:
       if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_LE:
       if (fs <= ft) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_ULE:
       if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_OR:
       if (!std::isnan(fs) && !std::isnan(ft)) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UNE:
       if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_NE:
       if (fs != ft) {
         set_fpu_register_word(fd_reg(), -1);
       } else {
         set_fpu_register_word(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterLRsType() {
   double fs = get_fpu_register_double(fs_reg());
   double ft = get_fpu_register_double(ft_reg());
   int64_t i64;
   switch (instr_.FunctionFieldRaw()) {
     case CVT_D_L:  // Mips32r2 instruction.
       i64 = get_fpu_register(fs_reg());
       set_fpu_register_double(fd_reg(), static_cast<double>(i64));
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     case CVT_S_L:
       i64 = get_fpu_register(fs_reg());
       set_fpu_register_float(fd_reg(), static_cast<float>(i64));
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     case CMP_AF:
       set_fpu_register(fd_reg(), 0);
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UN:
       if (std::isnan(fs) || std::isnan(ft)) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_EQ:
       if (fs == ft) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UEQ:
       if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_LT:
       if (fs < ft) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_ULT:
       if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_LE:
       if (fs <= ft) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_ULE:
       if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_OR:
       if (!std::isnan(fs) && !std::isnan(ft)) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_UNE:
       if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     case CMP_NE:
       if (fs != ft && (!std::isnan(fs) && !std::isnan(ft))) {
         set_fpu_register(fd_reg(), -1);
       } else {
         set_fpu_register(fd_reg(), 0);
       }
+      TraceRegWr(get_fpu_register(fd_reg()));
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterCOP1() {
   switch (instr_.RsFieldRaw()) {
     case BC1:  // Branch on coprocessor condition.
     case BC1EQZ:
     case BC1NEZ:
       UNREACHABLE();
       break;
     case CFC1:
       // At the moment only FCSR is supported.
       DCHECK(fs_reg() == kFCSRRegister);
       set_register(rt_reg(), FCSR_);
+      TraceRegWr(get_register(rt_reg()));
       break;
     case MFC1:
       set_register(rt_reg(),
                    static_cast<int64_t>(get_fpu_register_word(fs_reg())));
+      TraceRegWr(get_register(rt_reg()), WORD_DWORD);
       break;
     case DMFC1:
       set_register(rt_reg(), get_fpu_register(fs_reg()));
+      TraceRegWr(get_register(rt_reg()));
       break;
     case MFHC1:
       set_register(rt_reg(), get_fpu_register_hi_word(fs_reg()));
+      TraceRegWr(get_register(rt_reg()));
       break;
     case CTC1: {
       // At the moment only FCSR is supported.
       DCHECK(fs_reg() == kFCSRRegister);
       uint32_t reg = static_cast<uint32_t>(rt());
       if (kArchVariant == kMips64r6) {
         FCSR_ = reg | kFCSRNaN2008FlagMask;
       } else {
         DCHECK(kArchVariant == kMips64r2);
         FCSR_ = reg & ~kFCSRNaN2008FlagMask;
       }
+      TraceRegWr(FCSR_);
       break;
     }
     case MTC1:
       // Hardware writes upper 32-bits to zero on mtc1.
       set_fpu_register_hi_word(fs_reg(), 0);
       set_fpu_register_word(fs_reg(), static_cast<int32_t>(rt()));
+      TraceRegWr(get_fpu_register(fs_reg()), FLOAT_DOUBLE);
       break;
     case DMTC1:
       set_fpu_register(fs_reg(), rt());
+      TraceRegWr(get_fpu_register(fs_reg()), DOUBLE);
       break;
     case MTHC1:
       set_fpu_register_hi_word(fs_reg(), static_cast<int32_t>(rt()));
+      TraceRegWr(get_fpu_register(fs_reg()), DOUBLE);
       break;
     case S:
       DecodeTypeRegisterSRsType();
       break;
     case D:
       DecodeTypeRegisterDRsType();
       break;
     case W:
       DecodeTypeRegisterWRsType();
       break;
     case L:
       DecodeTypeRegisterLRsType();
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterCOP1X() {
   switch (instr_.FunctionFieldRaw()) {
     case MADD_S: {
       DCHECK(kArchVariant == kMips64r2);
       float fr, ft, fs;
       fr = get_fpu_register_float(fr_reg());
       fs = get_fpu_register_float(fs_reg());
       ft = get_fpu_register_float(ft_reg());
       set_fpu_register_float(fd_reg(), fs * ft + fr);
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     }
     case MSUB_S: {
       DCHECK(kArchVariant == kMips64r2);
       float fr, ft, fs;
       fr = get_fpu_register_float(fr_reg());
       fs = get_fpu_register_float(fs_reg());
       ft = get_fpu_register_float(ft_reg());
       set_fpu_register_float(fd_reg(), fs * ft - fr);
+      TraceRegWr(get_fpu_register(fd_reg()), FLOAT);
       break;
     }
     case MADD_D: {
       DCHECK(kArchVariant == kMips64r2);
       double fr, ft, fs;
       fr = get_fpu_register_double(fr_reg());
       fs = get_fpu_register_double(fs_reg());
       ft = get_fpu_register_double(ft_reg());
       set_fpu_register_double(fd_reg(), fs * ft + fr);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     case MSUB_D: {
       DCHECK(kArchVariant == kMips64r2);
       double fr, ft, fs;
       fr = get_fpu_register_double(fr_reg());
       fs = get_fpu_register_double(fs_reg());
       ft = get_fpu_register_double(ft_reg());
       set_fpu_register_double(fd_reg(), fs * ft - fr);
+      TraceRegWr(get_fpu_register(fd_reg()), DOUBLE);
       break;
     }
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::DecodeTypeRegisterSPECIAL() {
   int64_t i64hilo;
@@ skipping 1237 matching lines @@
       uint8_t al_offset = (rs + se_imm16) & kInt64AlignmentMask;
       uint64_t mask = (1UL << al_offset * 8) - 1;
       addr = rs + se_imm16 - al_offset;
       uint64_t mem_value = Read2W(addr, instr_.instr());
       mem_value = (rt << al_offset * 8) | (mem_value & mask);
       Write2W(addr, mem_value, instr_.instr());
       break;
     }
     case LWC1:
       set_fpu_register(ft_reg, kFPUInvalidResult);  // Trash upper 32 bits.
-      set_fpu_register_word(ft_reg, ReadW(rs + se_imm16, instr_.instr()));
+      set_fpu_register_word(ft_reg,
+                            ReadW(rs + se_imm16, instr_.instr(), FLOAT_DOUBLE));
       break;
     case LDC1:
       set_fpu_register_double(ft_reg, ReadD(rs + se_imm16, instr_.instr()));
+      TraceMemRd(addr, get_fpu_register(ft_reg), DOUBLE);
       break;
     case SWC1: {
       int32_t alu_out_32 = static_cast<int32_t>(get_fpu_register(ft_reg));
       WriteW(rs + se_imm16, alu_out_32, instr_.instr());
       break;
     }
     case SDC1:
       WriteD(rs + se_imm16, get_fpu_register_double(ft_reg), instr_.instr());
+      TraceMemWr(rs + se_imm16, get_fpu_register(ft_reg), DWORD);
       break;
     // ------------- PC-Relative instructions.
     case PCREL: {
       // rt field: checking 5-bits.
       int32_t imm21 = instr_.Imm21Value();
       int64_t current_pc = get_pc();
       uint8_t rt = (imm21 >> kImm16Bits);
       switch (rt) {
         case ALUIPC:
           addr = current_pc + (se_imm16 << 16);
@@ skipping 338 matching lines @@
 }
 
 
 #undef UNSUPPORTED
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS64