[ARM] Add vcge, vcgt instructions to assembler.

src/arm/simulator-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_ARM
 
@@ skipping 3822 matching lines @@
       if (instr->Bits(21, 20) == 2 && instr->Bits(11, 8) == 1 &&
           instr->Bit(4) == 1) {
         // vmov Qd, Qm
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         uint32_t data[4];
         get_q_register(Vm, data);
         set_q_register(Vd, data);
       } else if (instr->Bits(11, 8) == 8) {
         // vadd/vtst
-        int size = static_cast<NeonSize>(instr->Bits(21, 20));
+        NeonSize size = static_cast<NeonSize>(instr->Bits(21, 20));
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         int Vn = instr->VFPNRegValue(kSimd128Precision);
         if (instr->Bit(4) == 0) {
           // vadd.i<size> Qd, Qm, Qn.
           switch (size) {
             case Neon8: {
               uint8_t src1[16], src2[16];
               get_q_register(Vn, src1);
               get_q_register(Vm, src2);
@@ skipping 132 matching lines @@
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         int Vn = instr->VFPNRegValue(kSimd128Precision);
         float src1[4], src2[4];
         get_q_register(Vn, src1);
         get_q_register(Vm, src2);
         uint32_t dst[4];
         for (int i = 0; i < 4; i++) {
           dst[i] = (src1[i] == src2[i]) ? 0xFFFFFFFF : 0;
         }
         set_q_register(Vd, dst);
+      } else if (instr->Bits(11, 8) == 0x3) {
+        // vcge/vcgt.s<size> Qd, Qm, Qn.
+        bool ge = instr->Bit(4) == 1;
+        NeonSize size = static_cast<NeonSize>(instr->Bits(21, 20));
+        int Vd = instr->VFPDRegValue(kSimd128Precision);
+        int Vm = instr->VFPMRegValue(kSimd128Precision);
+        int Vn = instr->VFPNRegValue(kSimd128Precision);
+        switch (size) {
+          case Neon8: {
+            int8_t src1[16], src2[16];
+            get_q_register(Vn, src1);
+            get_q_register(Vm, src2);
+            for (int i = 0; i < 16; i++) {
+              if (ge)
+                src1[i] = src1[i] >= src2[i] ? 0xFF : 0;
+              else
+                src1[i] = src1[i] > src2[i] ? 0xFF : 0;
+            }
+            set_q_register(Vd, src1);
+            break;
+          }
+          case Neon16: {
+            int16_t src1[8], src2[8];
+            get_q_register(Vn, src1);
+            get_q_register(Vm, src2);
+            for (int i = 0; i < 8; i++) {
+              if (ge)
+                src1[i] = src1[i] >= src2[i] ? 0xFFFF : 0;
+              else
+                src1[i] = src1[i] > src2[i] ? 0xFFFF : 0;
+            }
+            set_q_register(Vd, src1);
+            break;
+          }
+          case Neon32: {
+            int32_t src1[4], src2[4];
+            get_q_register(Vn, src1);
+            get_q_register(Vm, src2);
+            for (int i = 0; i < 4; i++) {
+              if (ge)
+                src1[i] = src1[i] >= src2[i] ? 0xFFFFFFFF : 0;
+              else
+                src1[i] = src1[i] > src2[i] ? 0xFFFFFFFF : 0;
+            }
+            set_q_register(Vd, src1);
+            break;
+          }
+          default:
+            UNREACHABLE();
+            break;
+        }
       } else if (instr->Bit(20) == 0 && instr->Bits(11, 8) == 0xf &&
                  instr->Bit(6) == 1 && instr->Bit(4) == 1) {
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         int Vn = instr->VFPNRegValue(kSimd128Precision);
         float src1[4], src2[4];
         get_q_register(Vn, src1);
         get_q_register(Vm, src2);
         if (instr->Bit(21) == 0) {
           // vrecps.f32 Qd, Qm, Qn.
@@ skipping 49 matching lines @@
           dst[i] = src2[i - boundary];
         }
         set_q_register(Vd, dst);
       } else {
         UNIMPLEMENTED();
       }
       break;
     case 6:
       if (instr->Bits(11, 8) == 8 && instr->Bit(4) == 0) {
         // vsub.size Qd, Qm, Qn.
-        int size = static_cast<NeonSize>(instr->Bits(21, 20));
+        NeonSize size = static_cast<NeonSize>(instr->Bits(21, 20));
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         int Vn = instr->VFPNRegValue(kSimd128Precision);
         switch (size) {
           case Neon8: {
             uint8_t src1[16], src2[16];
             get_q_register(Vn, src1);
             get_q_register(Vm, src2);
             for (int i = 0; i < 16; i++) {
               src1[i] -= src2[i];
@@ skipping 20 matching lines @@
             }
             set_q_register(Vd, src1);
             break;
           }
           default:
             UNREACHABLE();
             break;
         }
       } else if (instr->Bits(11, 8) == 8 && instr->Bit(4) == 1) {
         // vceq.size Qd, Qm, Qn.
-        int size = static_cast<NeonSize>(instr->Bits(21, 20));
+        NeonSize size = static_cast<NeonSize>(instr->Bits(21, 20));
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         int Vn = instr->VFPNRegValue(kSimd128Precision);
         switch (size) {
           case Neon8: {
             uint8_t src1[16], src2[16];
             get_q_register(Vn, src1);
             get_q_register(Vm, src2);
             for (int i = 0; i < 16; i++) {
               src1[i] = (src1[i] == src2[i]) ? 0xFFu : 0;
@@ skipping 69 matching lines @@
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vn = instr->VFPNRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         float src1[4], src2[4];
         get_q_register(Vn, src1);
         get_q_register(Vm, src2);
         for (int i = 0; i < 4; i++) {
           src1[i] = src1[i] * src2[i];
         }
         set_q_register(Vd, src1);
+      } else if (instr->Bit(20) == 0 && instr->Bits(11, 8) == 0xe &&
+                 instr->Bit(4) == 0) {
+        // vcge/vcgt.f32 Qd, Qm, Qn
+        bool ge = instr->Bit(21) == 0;
+        int Vd = instr->VFPDRegValue(kSimd128Precision);
+        int Vm = instr->VFPMRegValue(kSimd128Precision);
+        int Vn = instr->VFPNRegValue(kSimd128Precision);
+        float src1[4], src2[4];
+        get_q_register(Vn, src1);
+        get_q_register(Vm, src2);
+        uint32_t dst[4];
+        for (int i = 0; i < 4; i++) {
+          if (ge) {
+            dst[i] = src1[i] >= src2[i] ? 0xFFFFFFFFu : 0;
+          } else {
+            dst[i] = src1[i] > src2[i] ? 0xFFFFFFFFu : 0;
+          }
+        }
+        set_q_register(Vd, dst);
+      } else if (instr->Bits(11, 8) == 0x3) {
+        // vcge/vcgt.u<size> Qd, Qm, Qn.
+        bool ge = instr->Bit(4) == 1;
+        NeonSize size = static_cast<NeonSize>(instr->Bits(21, 20));
+        int Vd = instr->VFPDRegValue(kSimd128Precision);
+        int Vm = instr->VFPMRegValue(kSimd128Precision);
+        int Vn = instr->VFPNRegValue(kSimd128Precision);
+        switch (size) {
+          case Neon8: {
+            uint8_t src1[16], src2[16];
+            get_q_register(Vn, src1);
+            get_q_register(Vm, src2);
+            for (int i = 0; i < 16; i++) {
+              if (ge)
+                src1[i] = src1[i] >= src2[i] ? 0xFFu : 0;
+              else
+                src1[i] = src1[i] > src2[i] ? 0xFFu : 0;
+            }
+            set_q_register(Vd, src1);
+            break;
+          }
+          case Neon16: {
+            uint16_t src1[8], src2[8];
+            get_q_register(Vn, src1);
+            get_q_register(Vm, src2);
+            for (int i = 0; i < 8; i++) {
+              if (ge)
+                src1[i] = src1[i] >= src2[i] ? 0xFFFFu : 0;
+              else
+                src1[i] = src1[i] > src2[i] ? 0xFFFFu : 0;
+            }
+            set_q_register(Vd, src1);
+            break;
+          }
+          case Neon32: {
+            uint32_t src1[4], src2[4];
+            get_q_register(Vn, src1);
+            get_q_register(Vm, src2);
+            for (int i = 0; i < 4; i++) {
+              if (ge)
+                src1[i] = src1[i] >= src2[i] ? 0xFFFFFFFFu : 0;
+              else
+                src1[i] = src1[i] > src2[i] ? 0xFFFFFFFFu : 0;
+            }
+            set_q_register(Vd, src1);
+            break;
+          }
+          default:
+            UNREACHABLE();
+            break;
+        }
       } else {
         UNIMPLEMENTED();
       }
       break;
     case 7:
       if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
           (instr->Bit(4) == 1)) {
         // vmovl unsigned
         if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
         int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
@@ skipping 101 matching lines @@
               result |=
                   ((table >> ((index % kDoubleSize) * kBitsPerByte)) & 0xFF)
                   << shift;
             } else if (vtbx) {
               result |= destination & (0xFFull << shift);
             }
           }
           set_d_register(vd, &result);
         } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 6) == 0x7) {
           // vzip.<size> Qd, Qm.
-          int size = static_cast<NeonSize>(instr->Bits(19, 18));
+          NeonSize size = static_cast<NeonSize>(instr->Bits(19, 18));
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           switch (size) {
             case Neon8: {
               uint8_t src1[16], src2[16], dst1[16], dst2[16];
               get_q_register(Vd, src1);
               get_q_register(Vm, src2);
               for (int i = 0; i < 8; i++) {
                 dst1[i * 2] = src1[i];
                 dst1[i * 2 + 1] = src2[i];
@@ skipping 33 matching lines @@
               break;
             }
             default:
               UNREACHABLE();
               break;
           }
         } else if (instr->Bits(17, 16) == 0 && instr->Bits(11, 9) == 0) {
           // vrev<op>.size Qd, Qm
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
-          int size = static_cast<NeonSize>(instr->Bits(19, 18));
+          NeonSize size = static_cast<NeonSize>(instr->Bits(19, 18));
           NeonSize op = static_cast<NeonSize>(static_cast<int>(Neon64) -
                                               instr->Bits(8, 7));
           switch (op) {
             case Neon16: {
               DCHECK_EQ(Neon8, size);
               uint8_t src[16];
               get_q_register(Vm, src);
               for (int i = 0; i < 16; i += 2) {
                 std::swap(src[i], src[i + 1]);
               }
@@ skipping 63 matching lines @@
               }
               break;
             }
             default:
               UNREACHABLE();
               break;
           }
         } else if (instr->Bits(17, 16) == 0x1 && instr->Bit(11) == 0) {
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
-          int size = static_cast<NeonSize>(instr->Bits(19, 18));
+          NeonSize size = static_cast<NeonSize>(instr->Bits(19, 18));
           if (instr->Bits(9, 6) == 0xd) {
             // vabs<type>.<size> Qd, Qm
             if (instr->Bit(10) != 0) {
               // floating point (clear sign bits)
               uint32_t src[4];
               get_q_register(Vm, src);
               for (int i = 0; i < 4; i++) {
                 src[i] &= ~0x80000000;
               }
               set_q_register(Vd, src);
@@ skipping 619 matching lines @@
   set_register(sp, current_sp + sizeof(uintptr_t));
   return address;
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_ARM