[ARM] Add vrecpe, vrecps, vrsqrte, vrsqrts instructions to assembler.

src/arm/simulator-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_ARM
 
@@ skipping 3979 matching lines @@
         int Vn = instr->VFPNRegValue(kSimd128Precision);
         uint32_t src1[4], src2[4];
         get_q_register(Vn, src1);
         get_q_register(Vm, src2);
         for (int i = 0; i < 4; i++) {
           src1[i] = bit_cast<float>(src1[i]) == bit_cast<float>(src2[i])
                         ? 0xFFFFFFFF
                         : 0;
         }
         set_q_register(Vd, src1);
-
+      } else if (instr->Bit(20) == 0 && instr->Bits(11, 8) == 0xf &&
+                 instr->Bit(6) == 1 && instr->Bit(4) == 1) {
+        int Vd = instr->VFPDRegValue(kSimd128Precision);
+        int Vm = instr->VFPMRegValue(kSimd128Precision);
+        int Vn = instr->VFPNRegValue(kSimd128Precision);
+        uint32_t src1[4], src2[4];
+        get_q_register(Vn, src1);
+        get_q_register(Vm, src2);
+        if (instr->Bit(21) == 0) {
+          // vrecps.f32 Qd, Qm, Qn.
+          for (int i = 0; i < 4; i++) {
+            src1[i] = bit_cast<uint32_t>(
+                2.0f - bit_cast<float>(src1[i]) * bit_cast<float>(src2[i]));
+          }
+        } else {
+          // vrsqrts.f32 Qd, Qm, Qn.
+          for (int i = 0; i < 4; i++) {
+            src1[i] = bit_cast<uint32_t>(
+                (3.0f - bit_cast<float>(src1[i]) * bit_cast<float>(src2[i])) /
+                2);
+          }
+        }
+        set_q_register(Vd, src1);
       } else {
         UNIMPLEMENTED();
       }
       break;
     case 5:
       if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
           (instr->Bit(4) == 1)) {
         // vmovl signed
         if ((instr->VdValue() & 1) != 0) UNIMPLEMENTED();
         int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
@@ skipping 489 matching lines @@
                 }
                 default:
                   UNIMPLEMENTED();
                   break;
               }
             }
           } else {
             UNIMPLEMENTED();
           }
           set_q_register(Vd, src);
+        } else if (instr->Bits(19, 18) == 0x2 && instr->Bits(11, 8) == 0x5) {
+          // vrecpe/vrsqrte.f32 Qd, Qm.
+          int Vd = instr->VFPDRegValue(kSimd128Precision);
+          int Vm = instr->VFPMRegValue(kSimd128Precision);
+          uint32_t src[4];
+          get_q_register(Vm, src);
+          if (instr->Bit(7) == 0) {
+            for (int i = 0; i < 4; i++) {
+              float denom = bit_cast<float>(src[i]);
+              div_zero_vfp_flag_ = (denom == 0);
+              float result = 1.0f / denom;
+              result = canonicalizeNaN(result);
+              src[i] = bit_cast<uint32_t>(result);
+            }
+          } else {
+            lazily_initialize_fast_sqrt(isolate_);
+            for (int i = 0; i < 4; i++) {
+              float radicand = bit_cast<float>(src[i]);
+              float result = 1.0f / fast_sqrt(radicand, isolate_);
+              result = canonicalizeNaN(result);
+              src[i] = bit_cast<uint32_t>(result);
+            }
+          }
+          set_q_register(Vd, src);
         } else {
           UNIMPLEMENTED();
         }
       } else {
         UNIMPLEMENTED();
       }
       break;
     case 8:
       if (instr->Bits(21, 20) == 0) {
         // vst1
@@ skipping 503 matching lines @@
   set_register(sp, current_sp + sizeof(uintptr_t));
   return address;
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_ARM