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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1893 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, | 1893 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, |
1894 "vmul.i%d q%d, q%d, q%d", size, Vd, Vn, Vm); | 1894 "vmul.i%d q%d, q%d, q%d", size, Vd, Vn, Vm); |
1895 } else if (instr->Bits(21, 20) == 0 && instr->Bits(11, 8) == 0xe && | 1895 } else if (instr->Bits(21, 20) == 0 && instr->Bits(11, 8) == 0xe && |
1896 instr->Bit(4) == 0) { | 1896 instr->Bit(4) == 0) { |
1897 int Vd = instr->VFPDRegValue(kSimd128Precision); | 1897 int Vd = instr->VFPDRegValue(kSimd128Precision); |
1898 int Vm = instr->VFPMRegValue(kSimd128Precision); | 1898 int Vm = instr->VFPMRegValue(kSimd128Precision); |
1899 int Vn = instr->VFPNRegValue(kSimd128Precision); | 1899 int Vn = instr->VFPNRegValue(kSimd128Precision); |
1900 // vceq.f32 Qd, Qm, Qn. | 1900 // vceq.f32 Qd, Qm, Qn. |
1901 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, | 1901 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, |
1902 "vceq.f32 q%d, q%d, q%d", Vd, Vn, Vm); | 1902 "vceq.f32 q%d, q%d, q%d", Vd, Vn, Vm); |
| 1903 } else if (instr->Bit(20) == 0 && instr->Bits(11, 8) == 0xf && |
| 1904 instr->Bit(6) == 1 && instr->Bit(4) == 1) { |
| 1905 int Vd = instr->VFPDRegValue(kSimd128Precision); |
| 1906 int Vm = instr->VFPMRegValue(kSimd128Precision); |
| 1907 int Vn = instr->VFPNRegValue(kSimd128Precision); |
| 1908 const char* op = instr->Bit(21) == 0 ? "vrecps" : "vrsqrts"; |
| 1909 // vrecps/vrsqrts.f32 Qd, Qm, Qn. |
| 1910 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, |
| 1911 "%s.f32 q%d, q%d, q%d", op, Vd, Vn, Vm); |
1903 } else { | 1912 } else { |
1904 Unknown(instr); | 1913 Unknown(instr); |
1905 } | 1914 } |
1906 break; | 1915 break; |
1907 case 5: | 1916 case 5: |
1908 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && | 1917 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && |
1909 (instr->Bit(4) == 1)) { | 1918 (instr->Bit(4) == 1)) { |
1910 // vmovl signed | 1919 // vmovl signed |
1911 if ((instr->VdValue() & 1) != 0) Unknown(instr); | 1920 if ((instr->VdValue() & 1) != 0) Unknown(instr); |
1912 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); | 1921 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); |
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2075 SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%s%d q%d, q%d", | 2084 SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%s%d q%d, q%d", |
2076 type, size, Vd, Vm); | 2085 type, size, Vd, Vm); |
2077 } else if (instr->Bits(9, 6) == 0xf) { | 2086 } else if (instr->Bits(9, 6) == 0xf) { |
2078 // vneg<type>.<size> Qd, Qm. | 2087 // vneg<type>.<size> Qd, Qm. |
2079 out_buffer_pos_ += | 2088 out_buffer_pos_ += |
2080 SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%s%d q%d, q%d", | 2089 SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%s%d q%d, q%d", |
2081 type, size, Vd, Vm); | 2090 type, size, Vd, Vm); |
2082 } else { | 2091 } else { |
2083 Unknown(instr); | 2092 Unknown(instr); |
2084 } | 2093 } |
| 2094 } else if (instr->Bits(19, 18) == 0x2 && instr->Bits(11, 8) == 0x5) { |
| 2095 int Vd = instr->VFPDRegValue(kSimd128Precision); |
| 2096 int Vm = instr->VFPMRegValue(kSimd128Precision); |
| 2097 const char* op = instr->Bit(7) == 0 ? "vrecpe" : "vrsqrte"; |
| 2098 // vrecpe/vrsqrte.f32 Qd, Qm. |
| 2099 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, |
| 2100 "%s.f32 q%d, q%d", op, Vd, Vm); |
2085 } else { | 2101 } else { |
2086 Unknown(instr); | 2102 Unknown(instr); |
2087 } | 2103 } |
2088 } else { | 2104 } else { |
2089 Unknown(instr); | 2105 Unknown(instr); |
2090 } | 2106 } |
2091 break; | 2107 break; |
2092 case 8: | 2108 case 8: |
2093 if (instr->Bits(21, 20) == 0) { | 2109 if (instr->Bits(21, 20) == 0) { |
2094 // vst1 | 2110 // vst1 |
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2423 pc += d.InstructionDecode(buffer, pc); | 2439 pc += d.InstructionDecode(buffer, pc); |
2424 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), | 2440 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), |
2425 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 2441 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
2426 } | 2442 } |
2427 } | 2443 } |
2428 | 2444 |
2429 | 2445 |
2430 } // namespace disasm | 2446 } // namespace disasm |
2431 | 2447 |
2432 #endif // V8_TARGET_ARCH_ARM | 2448 #endif // V8_TARGET_ARCH_ARM |
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