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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
(...skipping 4223 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
4234 dst.split_code(&vd, &d); | 4234 dst.split_code(&vd, &d); |
4235 int vn, n; | 4235 int vn, n; |
4236 src1.split_code(&vn, &n); | 4236 src1.split_code(&vn, &n); |
4237 int vm, m; | 4237 int vm, m; |
4238 src2.split_code(&vm, &m); | 4238 src2.split_code(&vm, &m); |
4239 int sz = static_cast<int>(size); | 4239 int sz = static_cast<int>(size); |
4240 emit(0x1E4U * B23 | d * B22 | sz * B20 | vn * B16 | vd * B12 | 0x9 * B8 | | 4240 emit(0x1E4U * B23 | d * B22 | sz * B20 | vn * B16 | vd * B12 | 0x9 * B8 | |
4241 n * B7 | B6 | m * B5 | B4 | vm); | 4241 n * B7 | B6 | m * B5 | B4 | vm); |
4242 } | 4242 } |
4243 | 4243 |
4244 void Assembler::vrecpe(const QwNeonRegister dst, const QwNeonRegister src) { | |
4245 DCHECK(IsEnabled(NEON)); | |
4246 // Qd = vadd(Qn, Qm) SIMD reciprocal estimate. | |
martyn.capewell
2017/01/06 17:48:51
It would be worth commenting that these estimate (
bbudge
2017/01/10 11:00:00
Done.
| |
4247 // Instruction details available in ARM DDI 0406C.b, A8-1024. | |
4248 int vd, d; | |
4249 dst.split_code(&vd, &d); | |
4250 int vm, m; | |
4251 src.split_code(&vm, &m); | |
4252 emit(0x1E7U * B23 | d * B22 | 0x3B * B16 | vd * B12 | 0x5 * B8 | B6 | m * B5 | | |
4253 vm); | |
4254 } | |
4255 | |
4256 void Assembler::vrecps(const QwNeonRegister dst, const QwNeonRegister src1, | |
4257 const QwNeonRegister src2) { | |
4258 DCHECK(IsEnabled(NEON)); | |
4259 // Qd = vadd(Qn, Qm) SIMD reciprocal refinement step. | |
4260 // Instruction details available in ARM DDI 0406C.b, A8-1026. | |
4261 int vd, d; | |
4262 dst.split_code(&vd, &d); | |
4263 int vn, n; | |
4264 src1.split_code(&vn, &n); | |
4265 int vm, m; | |
4266 src2.split_code(&vm, &m); | |
4267 emit(0x1E4U * B23 | d * B22 | vn * B16 | vd * B12 | 0xF * B8 | n * B7 | B6 | | |
4268 m * B5 | B4 | vm); | |
4269 } | |
4270 | |
4271 void Assembler::vrsqrte(const QwNeonRegister dst, const QwNeonRegister src) { | |
4272 DCHECK(IsEnabled(NEON)); | |
4273 // Qd = vadd(Qn, Qm) SIMD reciprocal square root estimate. | |
4274 // Instruction details available in ARM DDI 0406C.b, A8-1038. | |
4275 int vd, d; | |
4276 dst.split_code(&vd, &d); | |
4277 int vm, m; | |
4278 src.split_code(&vm, &m); | |
4279 emit(0x1E7U * B23 | d * B22 | 0x3B * B16 | vd * B12 | 0x5 * B8 | 0x3 * B6 | | |
4280 m * B5 | vm); | |
4281 } | |
4282 | |
4283 void Assembler::vrsqrts(const QwNeonRegister dst, const QwNeonRegister src1, | |
4284 const QwNeonRegister src2) { | |
4285 DCHECK(IsEnabled(NEON)); | |
4286 // Qd = vadd(Qn, Qm) SIMD reciprocal square root refinement step. | |
4287 // Instruction details available in ARM DDI 0406C.b, A8-1040. | |
4288 int vd, d; | |
4289 dst.split_code(&vd, &d); | |
4290 int vn, n; | |
4291 src1.split_code(&vn, &n); | |
4292 int vm, m; | |
4293 src2.split_code(&vm, &m); | |
4294 emit(0x1E4U * B23 | d * B22 | B21 | vn * B16 | vd * B12 | 0xF * B8 | n * B7 | | |
4295 B6 | m * B5 | B4 | vm); | |
4296 } | |
4297 | |
4244 void Assembler::vtst(NeonSize size, QwNeonRegister dst, | 4298 void Assembler::vtst(NeonSize size, QwNeonRegister dst, |
4245 const QwNeonRegister src1, const QwNeonRegister src2) { | 4299 const QwNeonRegister src1, const QwNeonRegister src2) { |
4246 DCHECK(IsEnabled(NEON)); | 4300 DCHECK(IsEnabled(NEON)); |
4247 // Qd = vtst(Qn, Qm) SIMD test integer operands. | 4301 // Qd = vtst(Qn, Qm) SIMD test integer operands. |
4248 // Instruction details available in ARM DDI 0406C.b, A8-1098. | 4302 // Instruction details available in ARM DDI 0406C.b, A8-1098. |
4249 int vd, d; | 4303 int vd, d; |
4250 dst.split_code(&vd, &d); | 4304 dst.split_code(&vd, &d); |
4251 int vn, n; | 4305 int vn, n; |
4252 src1.split_code(&vn, &n); | 4306 src1.split_code(&vn, &n); |
4253 int vm, m; | 4307 int vm, m; |
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4944 DCHECK(is_uint12(offset)); | 4998 DCHECK(is_uint12(offset)); |
4945 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); | 4999 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); |
4946 } | 5000 } |
4947 } | 5001 } |
4948 | 5002 |
4949 | 5003 |
4950 } // namespace internal | 5004 } // namespace internal |
4951 } // namespace v8 | 5005 } // namespace v8 |
4952 | 5006 |
4953 #endif // V8_TARGET_ARCH_ARM | 5007 #endif // V8_TARGET_ARCH_ARM |
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