[ARM] Add vrecpe, vrecps, vrsqrte, vrsqrts instructions to assembler.

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1881 matching lines @@
         out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                     "vmul.i%d q%d, q%d, q%d", size, Vd, Vn, Vm);
       } else if (instr->Bits(21, 20) == 0 && instr->Bits(11, 8) == 0xe &&
                  instr->Bit(4) == 0) {
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         int Vn = instr->VFPNRegValue(kSimd128Precision);
         // vceq.f32 Qd, Qm, Qn.
         out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                     "vceq.f32 q%d, q%d, q%d", Vd, Vn, Vm);
+      } else if (instr->Bit(20) == 0 && instr->Bits(11, 8) == 0xf &&
+                 instr->Bit(6) == 1 && instr->Bit(4) == 1) {
+        int Vd = instr->VFPDRegValue(kSimd128Precision);
+        int Vm = instr->VFPMRegValue(kSimd128Precision);
+        int Vn = instr->VFPNRegValue(kSimd128Precision);
+        const char* op = instr->Bit(21) == 0 ? "vrecps" : "vrsqrts";
+        // vrecps/vrsqrts.f32 Qd, Qm, Qn.
+        out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                    "%s.f32 q%d, q%d, q%d", op, Vd, Vn, Vm);
       } else {
         Unknown(instr);
       }
       break;
     case 5:
       if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
           (instr->Bit(4) == 1)) {
         // vmovl signed
         if ((instr->VdValue() & 1) != 0) Unknown(instr);
         int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
@@ skipping 162 matching lines @@
                 SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%s%d q%d, q%d",
                          type, size, Vd, Vm);
           } else if (instr->Bits(9, 6) == 0xf) {
             // vneg<type>.<size> Qd, Qm.
             out_buffer_pos_ +=
                 SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%s%d q%d, q%d",
                          type, size, Vd, Vm);
           } else {
             Unknown(instr);
           }
+        } else if (instr->Bits(19, 18) == 0x2 && instr->Bits(11, 8) == 0x5) {
+          int Vd = instr->VFPDRegValue(kSimd128Precision);
+          int Vm = instr->VFPMRegValue(kSimd128Precision);
+          const char* op = instr->Bit(7) == 0 ? "vrecpe" : "vrsqrte";
+          // vrecpe/vrsqrte.f32 Qd, Qm.
+          out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "%s.f32 q%d, q%d", op, Vd, Vm);
         } else {
           Unknown(instr);
         }
       } else {
         Unknown(instr);
       }
       break;
     case 8:
       if (instr->Bits(21, 20) == 0) {
         // vst1
@@ skipping 328 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM