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Unified Diff: src/arm64/assembler-arm64.cc

Issue 260003006: Added a Isolate* parameter to Serializer::enabled(). (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Rebased. Feedback. Created 6 years, 8 months ago
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Index: src/arm64/assembler-arm64.cc
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index 91b7638ed1cf7144e4dd69799d9acb652baa195b..14f4145578f176e3049b46e961d901ce65115111 100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -271,9 +271,9 @@ void Operand::initialize_handle(Handle<Object> handle) {
}
-bool Operand::NeedsRelocation() const {
+bool Operand::NeedsRelocation(Isolate* isolate) const {
if (rmode_ == RelocInfo::EXTERNAL_REFERENCE) {
- return Serializer::enabled();
+ return Serializer::enabled(isolate);
}
return !RelocInfo::IsNone(rmode_);
@@ -1903,7 +1903,7 @@ void Assembler::AddSub(const Register& rd,
FlagsUpdate S,
AddSubOp op) {
ASSERT(rd.SizeInBits() == rn.SizeInBits());
- ASSERT(!operand.NeedsRelocation());
+ ASSERT(!operand.NeedsRelocation(isolate()));
if (operand.IsImmediate()) {
int64_t immediate = operand.immediate();
ASSERT(IsImmAddSub(immediate));
@@ -1943,7 +1943,7 @@ void Assembler::AddSubWithCarry(const Register& rd,
ASSERT(rd.SizeInBits() == rn.SizeInBits());
ASSERT(rd.SizeInBits() == operand.reg().SizeInBits());
ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
- ASSERT(!operand.NeedsRelocation());
+ ASSERT(!operand.NeedsRelocation(isolate()));
Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
}
@@ -1964,7 +1964,7 @@ void Assembler::debug(const char* message, uint32_t code, Instr params) {
#ifdef USE_SIMULATOR
// Don't generate simulator specific code if we are building a snapshot, which
// might be run on real hardware.
- if (!Serializer::enabled()) {
+ if (!Serializer::enabled(isolate())) {
// The arguments to the debug marker need to be contiguous in memory, so
// make sure we don't try to emit pools.
BlockPoolsScope scope(this);
@@ -1999,7 +1999,7 @@ void Assembler::Logical(const Register& rd,
const Operand& operand,
LogicalOp op) {
ASSERT(rd.SizeInBits() == rn.SizeInBits());
- ASSERT(!operand.NeedsRelocation());
+ ASSERT(!operand.NeedsRelocation(isolate()));
if (operand.IsImmediate()) {
int64_t immediate = operand.immediate();
unsigned reg_size = rd.SizeInBits();
@@ -2051,7 +2051,7 @@ void Assembler::ConditionalCompare(const Register& rn,
Condition cond,
ConditionalCompareOp op) {
Instr ccmpop;
- ASSERT(!operand.NeedsRelocation());
+ ASSERT(!operand.NeedsRelocation(isolate()));
if (operand.IsImmediate()) {
int64_t immediate = operand.immediate();
ASSERT(IsImmConditionalCompare(immediate));
@@ -2166,7 +2166,7 @@ void Assembler::DataProcShiftedRegister(const Register& rd,
Instr op) {
ASSERT(operand.IsShiftedRegister());
ASSERT(rn.Is64Bits() || (rn.Is32Bits() && is_uint5(operand.shift_amount())));
- ASSERT(!operand.NeedsRelocation());
+ ASSERT(!operand.NeedsRelocation(isolate()));
Emit(SF(rd) | op | Flags(S) |
ShiftDP(operand.shift()) | ImmDPShift(operand.shift_amount()) |
Rm(operand.reg()) | Rn(rn) | Rd(rd));
@@ -2178,7 +2178,7 @@ void Assembler::DataProcExtendedRegister(const Register& rd,
const Operand& operand,
FlagsUpdate S,
Instr op) {
- ASSERT(!operand.NeedsRelocation());
+ ASSERT(!operand.NeedsRelocation(isolate()));
Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd);
Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
ExtendMode(operand.extend()) | ImmExtendShift(operand.shift_amount()) |
@@ -2517,7 +2517,7 @@ void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
if (!RelocInfo::IsNone(rmode)) {
// Don't record external references unless the heap will be serialized.
if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
- if (!Serializer::enabled() && !emit_debug_code()) {
+ if (!Serializer::enabled(isolate()) && !emit_debug_code()) {
return;
}
}
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