Added a Isolate* parameter to Serializer::enabled().

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1058 matching lines @@
     }
   }
   return false;
 }
 
 
 // We have to use the temporary register for things that can be relocated even
 // if they can be encoded in the ARM's 12 bits of immediate-offset instruction
 // space.  There is no guarantee that the relocated location can be similarly
 // encoded.
-bool Operand::must_output_reloc_info(const Assembler* assembler) const {
+bool Operand::must_output_reloc_info(Isolate* isolate,
+                                     const Assembler* assembler) const {
   if (rmode_ == RelocInfo::EXTERNAL_REFERENCE) {
     if (assembler != NULL && assembler->predictable_code_size()) return true;
-    return Serializer::enabled();
+    return Serializer::enabled(isolate);
   } else if (RelocInfo::IsNone(rmode_)) {
     return false;
   }
   return true;
 }
 
 
-static bool use_mov_immediate_load(const Operand& x,
+static bool use_mov_immediate_load(Isolate* isolate,
+                                   const Operand& x,
                                    const Assembler* assembler) {
   if (assembler != NULL && !assembler->can_use_constant_pool()) {
     // If there is no constant pool available, we must use an mov immediate.
     // TODO(rmcilroy): enable ARMv6 support.
     ASSERT(CpuFeatures::IsSupported(ARMv7));
     return true;
   } else if (CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS) &&
              (assembler == NULL || !assembler->predictable_code_size())) {
     // Prefer movw / movt to constant pool if it is more efficient on the CPU.
     return true;
-  } else if (x.must_output_reloc_info(assembler)) {
+  } else if (x.must_output_reloc_info(isolate, assembler)) {
     // Prefer constant pool if data is likely to be patched.
     return false;
   } else {
     // Otherwise, use immediate load if movw / movt is available.
     return CpuFeatures::IsSupported(ARMv7);
   }
 }
 
 
-bool Operand::is_single_instruction(const Assembler* assembler,
+bool Operand::is_single_instruction(Isolate* isolate,
+                                    const Assembler* assembler,
                                     Instr instr) const {
   if (rm_.is_valid()) return true;
   uint32_t dummy1, dummy2;
-  if (must_output_reloc_info(assembler) ||
+  if (must_output_reloc_info(isolate, assembler) ||
       !fits_shifter(imm32_, &dummy1, &dummy2, &instr)) {
     // The immediate operand cannot be encoded as a shifter operand, or use of
     // constant pool is required. For a mov instruction not setting the
     // condition code additional instruction conventions can be used.
     if ((instr & ~kCondMask) == 13*B21) {  // mov, S not set
-      return !use_mov_immediate_load(*this, assembler);
+      return !use_mov_immediate_load(isolate, *this, assembler);
     } else {
       // If this is not a mov or mvn instruction there will always an additional
       // instructions - either mov or ldr. The mov might actually be two
       // instructions mov or movw followed by movt so including the actual
       // instruction two or three instructions will be generated.
       return false;
     }
   } else {
     // No use of constant pool and the immediate operand can be encoded as a
     // shifter operand.
     return true;
   }
 }
 
 
 void Assembler::move_32_bit_immediate(Register rd,
                                       const Operand& x,
                                       Condition cond) {
   RelocInfo rinfo(pc_, x.rmode_, x.imm32_, NULL);
-  if (x.must_output_reloc_info(this)) {
+  if (x.must_output_reloc_info(isolate(), this)) {
     RecordRelocInfo(rinfo);
   }
 
-  if (use_mov_immediate_load(x, this)) {
+  if (use_mov_immediate_load(isolate(), x, this)) {
     Register target = rd.code() == pc.code() ? ip : rd;
     // TODO(rmcilroy): add ARMv6 support for immediate loads.
     ASSERT(CpuFeatures::IsSupported(ARMv7));
-    if (!FLAG_enable_ool_constant_pool && x.must_output_reloc_info(this)) {
+    if (!FLAG_enable_ool_constant_pool &&
+        x.must_output_reloc_info(isolate(), this)) {
       // Make sure the movw/movt doesn't get separated.
       BlockConstPoolFor(2);
     }
     emit(cond | 0x30*B20 | target.code()*B12 |
          EncodeMovwImmediate(x.imm32_ & 0xffff));
     movt(target, static_cast<uint32_t>(x.imm32_) >> 16, cond);
     if (target.code() != rd.code()) {
       mov(rd, target, LeaveCC, cond);
     }
   } else {
     ASSERT(can_use_constant_pool());
     ConstantPoolAddEntry(rinfo);
     ldr(rd, MemOperand(FLAG_enable_ool_constant_pool ? pp : pc, 0), cond);
   }
 }
 
 
 void Assembler::addrmod1(Instr instr,
                          Register rn,
                          Register rd,
                          const Operand& x) {
   CheckBuffer();
   ASSERT((instr & ~(kCondMask | kOpCodeMask | S)) == 0);
   if (!x.rm_.is_valid()) {
     // Immediate.
     uint32_t rotate_imm;
     uint32_t immed_8;
-    if (x.must_output_reloc_info(this) ||
+    if (x.must_output_reloc_info(isolate(), this) ||
         !fits_shifter(x.imm32_, &rotate_imm, &immed_8, &instr)) {
       // The immediate operand cannot be encoded as a shifter operand, so load
       // it first to register ip and change the original instruction to use ip.
       // However, if the original instruction is a 'mov rd, x' (not setting the
       // condition code), then replace it with a 'ldr rd, [pc]'.
       CHECK(!rn.is(ip));  // rn should never be ip, or will be trashed
       Condition cond = Instruction::ConditionField(instr);
       if ((instr & ~kCondMask) == 13*B21) {  // mov, S not set
         move_32_bit_immediate(rd, x, cond);
       } else {
@@ skipping 661 matching lines @@
 
 
 void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
                     Condition cond) {
   ASSERT(fields >= B16 && fields < B20);  // at least one field set
   Instr instr;
   if (!src.rm_.is_valid()) {
     // Immediate.
     uint32_t rotate_imm;
     uint32_t immed_8;
-    if (src.must_output_reloc_info(this) ||
+    if (src.must_output_reloc_info(isolate(), this) ||
         !fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) {
       // Immediate operand cannot be encoded, load it first to register ip.
       move_32_bit_immediate(ip, src);
       msr(fields, Operand(ip), cond);
       return;
     }
     instr = I | rotate_imm*B8 | immed_8;
   } else {
     ASSERT(!src.rs_.is_valid() && src.shift_imm_ == 0);  // only rm allowed
     instr = src.rm_.code();
@@ skipping 1382 matching lines @@
 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
   RelocInfo rinfo(pc_, rmode, data, NULL);
   RecordRelocInfo(rinfo);
 }
 
 
 void Assembler::RecordRelocInfo(const RelocInfo& rinfo) {
   if (!RelocInfo::IsNone(rinfo.rmode())) {
     // Don't record external references unless the heap will be serialized.
     if (rinfo.rmode() == RelocInfo::EXTERNAL_REFERENCE) {
-      if (!Serializer::enabled() && !emit_debug_code()) {
+      if (!Serializer::enabled(isolate()) && !emit_debug_code()) {
         return;
       }
     }
     ASSERT(buffer_space() >= kMaxRelocSize);  // too late to grow buffer here
     if (rinfo.rmode() == RelocInfo::CODE_TARGET_WITH_ID) {
       RelocInfo reloc_info_with_ast_id(rinfo.pc(),
                                        rinfo.rmode(),
                                        RecordedAstId().ToInt(),
                                        NULL);
       ClearRecordedAstId();
@@ skipping 210 matching lines @@
       if (IsLdrPcImmediateOffset(instr) &&
           GetLdrRegisterImmediateOffset(instr) == 0) {
         int delta = pc_ - rinfo.pc() - kPcLoadDelta;
         ASSERT(is_uint12(delta));
         // 0 is the smallest delta:
         //   ldr rd, [pc, #0]
         //   constant pool marker
         //   data
 
         bool found = false;
-        if (!Serializer::enabled() && (rinfo.rmode() >= RelocInfo::CELL)) {
+        if (!Serializer::enabled(isolate()) &&
+            (rinfo.rmode() >= RelocInfo::CELL)) {
           for (int j = 0; j < i; j++) {
             RelocInfo& rinfo2 = pending_32_bit_reloc_info_[j];
 
             if ((rinfo2.data() == rinfo.data()) &&
                 (rinfo2.rmode() == rinfo.rmode())) {
               Instr instr2 = instr_at(rinfo2.pc());
               if (IsLdrPcImmediateOffset(instr2)) {
                 delta = GetLdrRegisterImmediateOffset(instr2);
                 delta += rinfo2.pc() - rinfo.pc();
                 found = true;
@@ skipping 83 matching lines @@
   RelocInfo::Mode rmode = rinfo.rmode();
   ASSERT(rmode != RelocInfo::COMMENT &&
          rmode != RelocInfo::POSITION &&
          rmode != RelocInfo::STATEMENT_POSITION &&
          rmode != RelocInfo::CONST_POOL);
 
 
   // Try to merge entries which won't be patched.
   int merged_index = -1;
   if (RelocInfo::IsNone(rmode) ||
-      (!Serializer::enabled() && (rmode >= RelocInfo::CELL))) {
+      (!Serializer::enabled(assm->isolate()) && (rmode >= RelocInfo::CELL))) {
     size_t i;
     std::vector<RelocInfo>::const_iterator it;
     for (it = entries_.begin(), i = 0; it != entries_.end(); it++, i++) {
       if (RelocInfo::IsEqual(rinfo, *it)) {
         merged_index = i;
         break;
       }
     }
   }
 
@@ skipping 115 matching lines @@
   ASSERT((index_64bit == count_of_64bit_) &&
          (index_code_ptr == (index_64bit + count_of_code_ptr_)) &&
          (index_heap_ptr == (index_code_ptr + count_of_heap_ptr_)) &&
          (index_32bit == (index_heap_ptr + count_of_32bit_)));
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM