Enables all codegen tests for arm64.

runtime/vm/assembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 410 matching lines @@
     LoadWordFromPoolOffset(dst, pp, offset);
   } else {
     ASSERT((Isolate::Current() == Dart::vm_isolate()) ||
            object.IsSmi() ||
            object.InVMHeap());
     LoadDecodableImmediate(dst, reinterpret_cast<int64_t>(object.raw()), pp);
   }
 }
 
 
+void Assembler::CompareObject(Register reg, const Object& object, Register pp) {
+  if (CanLoadObjectFromPool(object)) {
+    LoadObject(TMP, object, pp);
+    CompareRegisters(reg, TMP);
+  } else {
+    CompareImmediate(
+        reg, reinterpret_cast<int64_t>(object.raw()), pp);

[regis, 2014/04/25 21:17:51]

one line

[zra, 2014/04/25 21:28:28]

Done.

+  }
+}
+
+
 void Assembler::LoadDecodableImmediate(Register reg, int64_t imm, Register pp) {
   if ((pp != kNoRegister) && (Isolate::Current() != Dart::vm_isolate())) {
     int64_t val_smi_tag = imm & kSmiTagMask;
     imm &= ~kSmiTagMask;  // Mask off the tag bits.
     const int32_t offset = Array::element_offset(FindImmediate(imm));
     LoadWordFromPoolOffset(reg, pp, offset);
     if (val_smi_tag != 0) {
       // Add back the tag bits.
       orri(reg, reg, val_smi_tag);
     }
@@ skipping 122 matching lines @@
   } else if (Operand::CanHold(-imm, kXRegSizeInBits, &op) ==
              Operand::Immediate) {
     sub(dest, rn, op);
   } else {
     LoadImmediate(TMP2, imm, pp);
     add(dest, rn, Operand(TMP2));
   }
 }
 
 
+void Assembler::TestImmediate(Register rn, int64_t imm, Register pp) {
+  Operand imm_op;
+  if (Operand::IsImmLogical(imm, kXRegSizeInBits, &imm_op)) {
+    tsti(rn, imm);
+  } else {
+    LoadImmediate(TMP, imm, pp);
+    tst(rn, Operand(TMP));
+  }
+}
+
+
 void Assembler::CompareImmediate(Register rn, int64_t imm, Register pp) {
   ASSERT(rn != TMP2);
   Operand op;
   if (Operand::CanHold(imm, kXRegSizeInBits, &op) == Operand::Immediate) {
     cmp(rn, op);
   } else if (Operand::CanHold(-imm, kXRegSizeInBits, &op) ==
              Operand::Immediate) {
     cmn(rn, op);
   } else {
     LoadImmediate(TMP2, imm, pp);
@@ skipping 307 matching lines @@
 }
 
 
 void Assembler::LeaveStubFrame() {
   // Restore and untag PP.
   LoadFromOffset(PP, FP, kSavedCallerPpSlotFromFp * kWordSize);
   sub(PP, PP, Operand(kHeapObjectTag));
   LeaveFrame();
 }
 
+
+void Assembler::UpdateAllocationStats(intptr_t cid,
+                                      Register temp_reg,
+                                      Heap::Space space) {
+  ASSERT(temp_reg != kNoRegister);
+  ASSERT(temp_reg != TMP);
+  ASSERT(cid > 0);
+  Isolate* isolate = Isolate::Current();
+  ClassTable* class_table = isolate->class_table();
+  if (cid < kNumPredefinedCids) {
+    const uword class_heap_stats_table_address =
+        class_table->PredefinedClassHeapStatsTableAddress();
+    const uword class_offset = cid * sizeof(ClassHeapStats);  // NOLINT
+    const uword count_field_offset = (space == Heap::kNew) ?
+      ClassHeapStats::allocated_since_gc_new_space_offset() :
+      ClassHeapStats::allocated_since_gc_old_space_offset();
+    LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset, PP);
+    const Address& count_address = Address(temp_reg, count_field_offset);
+    ldr(TMP, count_address);
+    AddImmediate(TMP, TMP, 1, PP);
+    str(TMP, count_address);
+  } else {
+    ASSERT(temp_reg != kNoRegister);
+    const uword class_offset = cid * sizeof(ClassHeapStats);  // NOLINT
+    const uword count_field_offset = (space == Heap::kNew) ?
+      ClassHeapStats::allocated_since_gc_new_space_offset() :
+      ClassHeapStats::allocated_since_gc_old_space_offset();
+    LoadImmediate(temp_reg, class_table->ClassStatsTableAddress(), PP);
+    ldr(temp_reg, Address(temp_reg));
+    AddImmediate(temp_reg, temp_reg, class_offset, PP);
+    ldr(TMP, Address(temp_reg, count_field_offset));
+    AddImmediate(TMP, TMP, 1, PP);
+    str(TMP, Address(temp_reg, count_field_offset));
+  }
+}
+
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64