OLD | NEW |
1 // | 1 // |
2 // The Subzero Code Generator | 2 // The Subzero Code Generator |
3 // | 3 // |
4 // This file is distributed under the University of Illinois Open Source | 4 // This file is distributed under the University of Illinois Open Source |
5 // License. See LICENSE.TXT for details. | 5 // License. See LICENSE.TXT for details. |
6 // | 6 // |
7 //===----------------------------------------------------------------------===// | 7 //===----------------------------------------------------------------------===// |
8 /// | 8 /// |
9 /// \file | 9 /// \file |
10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost | 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost |
(...skipping 1278 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1289 } | 1289 } |
1290 } | 1290 } |
1291 Context.insert<InstAssign>(Arg, RegisterArg); | 1291 Context.insert<InstAssign>(Arg, RegisterArg); |
1292 } | 1292 } |
1293 | 1293 |
1294 // Insert fake use of ImplicitRet_v4f32 to keep it live | 1294 // Insert fake use of ImplicitRet_v4f32 to keep it live |
1295 if (ImplicitRetVec) { | 1295 if (ImplicitRetVec) { |
1296 for (CfgNode *Node : Func->getNodes()) { | 1296 for (CfgNode *Node : Func->getNodes()) { |
1297 for (Inst &Instr : Node->getInsts()) { | 1297 for (Inst &Instr : Node->getInsts()) { |
1298 if (llvm::isa<InstRet>(&Instr)) { | 1298 if (llvm::isa<InstRet>(&Instr)) { |
1299 Context.setInsertPoint(Instr); | 1299 Context.setInsertPoint(instToIterator(&Instr)); |
1300 Context.insert<InstFakeUse>(ImplicitRetVec); | 1300 Context.insert<InstFakeUse>(ImplicitRetVec); |
1301 break; | 1301 break; |
1302 } | 1302 } |
1303 } | 1303 } |
1304 } | 1304 } |
1305 } | 1305 } |
1306 } | 1306 } |
1307 | 1307 |
1308 Type TargetMIPS32::stackSlotType() { return IceType_i32; } | 1308 Type TargetMIPS32::stackSlotType() { return IceType_i32; } |
1309 | 1309 |
(...skipping 4666 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
5976 if (auto *CallTargetR = llvm::dyn_cast<Variable>(CallTarget)) { | 5976 if (auto *CallTargetR = llvm::dyn_cast<Variable>(CallTarget)) { |
5977 Variable *T6 = Target->getPhysicalRegister(RegMIPS32::Reg_T6); | 5977 Variable *T6 = Target->getPhysicalRegister(RegMIPS32::Reg_T6); |
5978 Target->_and(CallTargetR, CallTargetR, T6); | 5978 Target->_and(CallTargetR, CallTargetR, T6); |
5979 } | 5979 } |
5980 } | 5980 } |
5981 return Target->Context.insert<InstMIPS32Call>(ReturnReg, CallTarget); | 5981 return Target->Context.insert<InstMIPS32Call>(ReturnReg, CallTarget); |
5982 } | 5982 } |
5983 | 5983 |
5984 } // end of namespace MIPS32 | 5984 } // end of namespace MIPS32 |
5985 } // end of namespace Ice | 5985 } // end of namespace Ice |
OLD | NEW |