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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1063 #undef DECODE_VRR_C_INSTRUCTIONS | 1063 #undef DECODE_VRR_C_INSTRUCTIONS |
1064 case LLILF: | 1064 case LLILF: |
1065 Format(instr, "llilf\t'r1,'i7"); | 1065 Format(instr, "llilf\t'r1,'i7"); |
1066 break; | 1066 break; |
1067 case LLIHF: | 1067 case LLIHF: |
1068 Format(instr, "llihf\t'r1,'i7"); | 1068 Format(instr, "llihf\t'r1,'i7"); |
1069 break; | 1069 break; |
1070 case AFI: | 1070 case AFI: |
1071 Format(instr, "afi\t'r1,'i7"); | 1071 Format(instr, "afi\t'r1,'i7"); |
1072 break; | 1072 break; |
| 1073 case AIH: |
| 1074 Format(instr, "aih\t'r1,'i7"); |
| 1075 break; |
1073 case ASI: | 1076 case ASI: |
1074 Format(instr, "asi\t'd2('r3),'ic"); | 1077 Format(instr, "asi\t'd2('r3),'ic"); |
1075 break; | 1078 break; |
1076 case AGSI: | 1079 case AGSI: |
1077 Format(instr, "agsi\t'd2('r3),'ic"); | 1080 Format(instr, "agsi\t'd2('r3),'ic"); |
1078 break; | 1081 break; |
1079 case ALFI: | 1082 case ALFI: |
1080 Format(instr, "alfi\t'r1,'i7"); | 1083 Format(instr, "alfi\t'r1,'i7"); |
1081 break; | 1084 break; |
1082 case AHIK: | 1085 case AHIK: |
1083 Format(instr, "ahik\t'r1,'r2,'i1"); | 1086 Format(instr, "ahik\t'r1,'r2,'i1"); |
1084 break; | 1087 break; |
1085 case AGHIK: | 1088 case AGHIK: |
1086 Format(instr, "aghik\t'r1,'r2,'i1"); | 1089 Format(instr, "aghik\t'r1,'r2,'i1"); |
1087 break; | 1090 break; |
1088 case CLGFI: | 1091 case CLGFI: |
1089 Format(instr, "clgfi\t'r1,'i7"); | 1092 Format(instr, "clgfi\t'r1,'i7"); |
1090 break; | 1093 break; |
1091 case CLFI: | 1094 case CLFI: |
1092 Format(instr, "clfi\t'r1,'i7"); | 1095 Format(instr, "clfi\t'r1,'i7"); |
1093 break; | 1096 break; |
| 1097 case CLIH: |
| 1098 Format(instr, "clih\t'r1,'i7"); |
| 1099 break; |
| 1100 case CIH: |
| 1101 Format(instr, "cih\t'r1,'i2"); |
| 1102 break; |
1094 case CFI: | 1103 case CFI: |
1095 Format(instr, "cfi\t'r1,'i2"); | 1104 Format(instr, "cfi\t'r1,'i2"); |
1096 break; | 1105 break; |
1097 case CGFI: | 1106 case CGFI: |
1098 Format(instr, "cgfi\t'r1,'i2"); | 1107 Format(instr, "cgfi\t'r1,'i2"); |
1099 break; | 1108 break; |
1100 case BRASL: | 1109 case BRASL: |
1101 Format(instr, "brasl\t'r1,'ie"); | 1110 Format(instr, "brasl\t'r1,'ie"); |
1102 break; | 1111 break; |
1103 case BRCL: | 1112 case BRCL: |
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1483 byte* prev_pc = pc; | 1492 byte* prev_pc = pc; |
1484 pc += d.InstructionDecode(buffer, pc); | 1493 pc += d.InstructionDecode(buffer, pc); |
1485 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), | 1494 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), |
1486 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1495 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1487 } | 1496 } |
1488 } | 1497 } |
1489 | 1498 |
1490 } // namespace disasm | 1499 } // namespace disasm |
1491 | 1500 |
1492 #endif // V8_TARGET_ARCH_S390 | 1501 #endif // V8_TARGET_ARCH_S390 |
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