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Side by Side Diff: src/compiler/ia32/instruction-selector-ia32.cc

Issue 2593483002: [ia32] Optimize index calculation for certain checked load/stores. (Closed)
Patch Set: Rebase Created 3 years, 11 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/compiler/instruction-selector-impl.h" 6 #include "src/compiler/instruction-selector-impl.h"
7 #include "src/compiler/node-matchers.h" 7 #include "src/compiler/node-matchers.h"
8 #include "src/compiler/node-properties.h" 8 #include "src/compiler/node-properties.h"
9 9
10 namespace v8 { 10 namespace v8 {
(...skipping 377 matching lines...) Expand 10 before | Expand all | Expand 10 after
388 case MachineRepresentation::kBit: // Fall through. 388 case MachineRepresentation::kBit: // Fall through.
389 case MachineRepresentation::kTaggedSigned: // Fall through. 389 case MachineRepresentation::kTaggedSigned: // Fall through.
390 case MachineRepresentation::kTaggedPointer: // Fall through. 390 case MachineRepresentation::kTaggedPointer: // Fall through.
391 case MachineRepresentation::kTagged: // Fall through. 391 case MachineRepresentation::kTagged: // Fall through.
392 case MachineRepresentation::kWord64: // Fall through. 392 case MachineRepresentation::kWord64: // Fall through.
393 case MachineRepresentation::kSimd128: // Fall through. 393 case MachineRepresentation::kSimd128: // Fall through.
394 case MachineRepresentation::kNone: 394 case MachineRepresentation::kNone:
395 UNREACHABLE(); 395 UNREACHABLE();
396 return; 396 return;
397 } 397 }
398 if (offset->opcode() == IrOpcode::kInt32Add && CanCover(node, offset)) {
399 Int32BinopMatcher moffset(offset);
400 InstructionOperand buffer_operand = g.CanBeImmediate(buffer)
401 ? g.UseImmediate(buffer)
402 : g.UseRegister(buffer);
403 Int32Matcher mlength(length);
404 if (mlength.HasValue() && moffset.right().HasValue() &&
405 moffset.right().Value() >= 0 &&
406 mlength.Value() >= moffset.right().Value()) {
407 Emit(opcode, g.DefineAsRegister(node),
408 g.UseImmediate(moffset.right().node()), g.UseImmediate(length),
409 g.UseRegister(moffset.left().node()), buffer_operand);
410 return;
411 }
412 IntMatcher<int32_t, IrOpcode::kRelocatableInt32Constant> mmlength(length);
413 if (mmlength.HasValue() && moffset.right().HasValue() &&
414 moffset.right().Value() >= 0 &&
415 mmlength.Value() >= moffset.right().Value()) {
416 Emit(opcode, g.DefineAsRegister(node),
417 g.UseImmediate(moffset.right().node()), g.UseImmediate(length),
418 g.UseRegister(moffset.left().node()), buffer_operand);
419 return;
420 }
421 }
398 InstructionOperand offset_operand = g.UseRegister(offset); 422 InstructionOperand offset_operand = g.UseRegister(offset);
399 InstructionOperand length_operand = 423 InstructionOperand length_operand =
400 g.CanBeImmediate(length) ? g.UseImmediate(length) : g.UseRegister(length); 424 g.CanBeImmediate(length) ? g.UseImmediate(length) : g.UseRegister(length);
401 if (g.CanBeImmediate(buffer)) { 425 if (g.CanBeImmediate(buffer)) {
402 Emit(opcode | AddressingModeField::encode(kMode_MRI), 426 Emit(opcode | AddressingModeField::encode(kMode_MRI),
403 g.DefineAsRegister(node), offset_operand, length_operand, 427 g.DefineAsRegister(node), offset_operand, length_operand,
404 offset_operand, g.UseImmediate(buffer)); 428 offset_operand, g.UseImmediate(buffer));
405 } else { 429 } else {
406 Emit(opcode | AddressingModeField::encode(kMode_MR1), 430 Emit(opcode | AddressingModeField::encode(kMode_MR1),
407 g.DefineAsRegister(node), offset_operand, length_operand, 431 g.DefineAsRegister(node), offset_operand, length_operand,
(...skipping 35 matching lines...) Expand 10 before | Expand all | Expand 10 after
443 case MachineRepresentation::kNone: 467 case MachineRepresentation::kNone:
444 UNREACHABLE(); 468 UNREACHABLE();
445 return; 469 return;
446 } 470 }
447 InstructionOperand value_operand = 471 InstructionOperand value_operand =
448 g.CanBeImmediate(value) ? g.UseImmediate(value) 472 g.CanBeImmediate(value) ? g.UseImmediate(value)
449 : ((rep == MachineRepresentation::kWord8 || 473 : ((rep == MachineRepresentation::kWord8 ||
450 rep == MachineRepresentation::kBit) 474 rep == MachineRepresentation::kBit)
451 ? g.UseByteRegister(value) 475 ? g.UseByteRegister(value)
452 : g.UseRegister(value)); 476 : g.UseRegister(value));
477 if (offset->opcode() == IrOpcode::kInt32Add && CanCover(node, offset)) {
478 Int32BinopMatcher moffset(offset);
479 InstructionOperand buffer_operand = g.CanBeImmediate(buffer)
480 ? g.UseImmediate(buffer)
481 : g.UseRegister(buffer);
482 Int32Matcher mlength(length);
483 if (mlength.HasValue() && moffset.right().HasValue() &&
484 moffset.right().Value() >= 0 &&
485 mlength.Value() >= moffset.right().Value()) {
486 Emit(opcode, g.NoOutput(), g.UseImmediate(moffset.right().node()),
487 g.UseImmediate(length), value_operand,
488 g.UseRegister(moffset.left().node()), buffer_operand);
489 return;
490 }
491 IntMatcher<int32_t, IrOpcode::kRelocatableInt32Constant> mmlength(length);
492 if (mmlength.HasValue() && moffset.right().HasValue() &&
493 moffset.right().Value() >= 0 &&
494 mmlength.Value() >= moffset.right().Value()) {
495 Emit(opcode, g.NoOutput(), g.UseImmediate(moffset.right().node()),
496 g.UseImmediate(length), value_operand,
497 g.UseRegister(moffset.left().node()), buffer_operand);
498 return;
499 }
500 }
453 InstructionOperand offset_operand = g.UseRegister(offset); 501 InstructionOperand offset_operand = g.UseRegister(offset);
454 InstructionOperand length_operand = 502 InstructionOperand length_operand =
455 g.CanBeImmediate(length) ? g.UseImmediate(length) : g.UseRegister(length); 503 g.CanBeImmediate(length) ? g.UseImmediate(length) : g.UseRegister(length);
456 if (g.CanBeImmediate(buffer)) { 504 if (g.CanBeImmediate(buffer)) {
457 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(), 505 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
458 offset_operand, length_operand, value_operand, offset_operand, 506 offset_operand, length_operand, value_operand, offset_operand,
459 g.UseImmediate(buffer)); 507 g.UseImmediate(buffer));
460 } else { 508 } else {
461 Emit(opcode | AddressingModeField::encode(kMode_MR1), g.NoOutput(), 509 Emit(opcode | AddressingModeField::encode(kMode_MR1), g.NoOutput(),
462 offset_operand, length_operand, value_operand, g.UseRegister(buffer), 510 offset_operand, length_operand, value_operand, g.UseRegister(buffer),
(...skipping 1334 matching lines...) Expand 10 before | Expand all | Expand 10 after
1797 // static 1845 // static
1798 MachineOperatorBuilder::AlignmentRequirements 1846 MachineOperatorBuilder::AlignmentRequirements
1799 InstructionSelector::AlignmentRequirements() { 1847 InstructionSelector::AlignmentRequirements() {
1800 return MachineOperatorBuilder::AlignmentRequirements:: 1848 return MachineOperatorBuilder::AlignmentRequirements::
1801 FullUnalignedAccessSupport(); 1849 FullUnalignedAccessSupport();
1802 } 1850 }
1803 1851
1804 } // namespace compiler 1852 } // namespace compiler
1805 } // namespace internal 1853 } // namespace internal
1806 } // namespace v8 1854 } // namespace v8
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