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| 1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
| 6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
| 7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
| 8 // | 8 // |
| 9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
| 10 // | 10 // |
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| 1885 "%s.f32 q%d, q%d, q%d", op, Vd, Vn, Vm); | 1885 "%s.f32 q%d, q%d, q%d", op, Vd, Vn, Vm); |
| 1886 } else if (instr->Bits(11, 8) == 0x9 && instr->Bit(6) == 1 && | 1886 } else if (instr->Bits(11, 8) == 0x9 && instr->Bit(6) == 1 && |
| 1887 instr->Bit(4) == 1) { | 1887 instr->Bit(4) == 1) { |
| 1888 int size = kBitsPerByte * (1 << instr->Bits(21, 20)); | 1888 int size = kBitsPerByte * (1 << instr->Bits(21, 20)); |
| 1889 int Vd = instr->VFPDRegValue(kSimd128Precision); | 1889 int Vd = instr->VFPDRegValue(kSimd128Precision); |
| 1890 int Vm = instr->VFPMRegValue(kSimd128Precision); | 1890 int Vm = instr->VFPMRegValue(kSimd128Precision); |
| 1891 int Vn = instr->VFPNRegValue(kSimd128Precision); | 1891 int Vn = instr->VFPNRegValue(kSimd128Precision); |
| 1892 // vmul.i<size> Qd, Qm, Qn. | 1892 // vmul.i<size> Qd, Qm, Qn. |
| 1893 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, | 1893 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, |
| 1894 "vmul.i%d q%d, q%d, q%d", size, Vd, Vn, Vm); | 1894 "vmul.i%d q%d, q%d, q%d", size, Vd, Vn, Vm); |
| 1895 } else if (instr->Bits(21, 20) == 0 && instr->Bits(11, 8) == 0xe && |
| 1896 instr->Bit(4) == 0) { |
| 1897 int Vd = instr->VFPDRegValue(kSimd128Precision); |
| 1898 int Vm = instr->VFPMRegValue(kSimd128Precision); |
| 1899 int Vn = instr->VFPNRegValue(kSimd128Precision); |
| 1900 // vceq.f32 Qd, Qm, Qn. |
| 1901 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, |
| 1902 "vceq.f32 q%d, q%d, q%d", Vd, Vn, Vm); |
| 1895 } else { | 1903 } else { |
| 1896 Unknown(instr); | 1904 Unknown(instr); |
| 1897 } | 1905 } |
| 1898 break; | 1906 break; |
| 1899 case 5: | 1907 case 5: |
| 1900 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && | 1908 if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && |
| 1901 (instr->Bit(4) == 1)) { | 1909 (instr->Bit(4) == 1)) { |
| 1902 // vmovl signed | 1910 // vmovl signed |
| 1903 if ((instr->VdValue() & 1) != 0) Unknown(instr); | 1911 if ((instr->VdValue() & 1) != 0) Unknown(instr); |
| 1904 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); | 1912 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); |
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| 2415 pc += d.InstructionDecode(buffer, pc); | 2423 pc += d.InstructionDecode(buffer, pc); |
| 2416 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), | 2424 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), |
| 2417 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 2425 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
| 2418 } | 2426 } |
| 2419 } | 2427 } |
| 2420 | 2428 |
| 2421 | 2429 |
| 2422 } // namespace disasm | 2430 } // namespace disasm |
| 2423 | 2431 |
| 2424 #endif // V8_TARGET_ARCH_ARM | 2432 #endif // V8_TARGET_ARCH_ARM |
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