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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1002 // 0 8 16 20 32 36 40 47 | 1002 // 0 8 16 20 32 36 40 47 |
1003 #define SIY_FORM_EMIT(name, op) \ | 1003 #define SIY_FORM_EMIT(name, op) \ |
1004 void Assembler::name(const Operand& i2, Register b1, Disp d1) { \ | 1004 void Assembler::name(const Operand& i2, Register b1, Disp d1) { \ |
1005 siy_form(op, i2, b1, d1); \ | 1005 siy_form(op, i2, b1, d1); \ |
1006 } \ | 1006 } \ |
1007 void Assembler::name(const MemOperand& opnd, const Operand& i2) { \ | 1007 void Assembler::name(const MemOperand& opnd, const Operand& i2) { \ |
1008 name(i2, opnd.getBaseRegister(), opnd.getDisplacement()); \ | 1008 name(i2, opnd.getBaseRegister(), opnd.getDisplacement()); \ |
1009 } | 1009 } |
1010 | 1010 |
1011 void Assembler::siy_form(Opcode op, const Operand& i2, Register b1, Disp d1) { | 1011 void Assembler::siy_form(Opcode op, const Operand& i2, Register b1, Disp d1) { |
1012 DCHECK(is_uint20(d1)); | 1012 DCHECK(is_uint20(d1) || is_int20(d1)); |
1013 DCHECK(is_uint16(op)); | 1013 DCHECK(is_uint16(op)); |
1014 DCHECK(is_uint8(i2.imm_)); | 1014 DCHECK(is_uint8(i2.imm_)); |
1015 uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | | 1015 uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 | |
1016 (static_cast<uint64_t>(i2.imm_)) * B32 | | 1016 (static_cast<uint64_t>(i2.imm_)) * B32 | |
1017 (static_cast<uint64_t>(b1.code())) * B28 | | 1017 (static_cast<uint64_t>(b1.code())) * B28 | |
1018 (static_cast<uint64_t>(d1 & 0x0FFF)) * B16 | | 1018 (static_cast<uint64_t>(d1 & 0x0FFF)) * B16 | |
1019 (static_cast<uint64_t>(d1 & 0x0FF000)) >> 4 | | 1019 (static_cast<uint64_t>(d1 & 0x0FF000)) >> 4 | |
1020 (static_cast<uint64_t>(op & 0x00FF)); | 1020 (static_cast<uint64_t>(op & 0x00FF)); |
1021 emit6bytes(code); | 1021 emit6bytes(code); |
1022 } | 1022 } |
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2621 SKIP_ICACHE_FLUSH); | 2621 SKIP_ICACHE_FLUSH); |
2622 } | 2622 } |
2623 | 2623 |
2624 reloc_info_writer.Write(&rinfo); | 2624 reloc_info_writer.Write(&rinfo); |
2625 } | 2625 } |
2626 } | 2626 } |
2627 | 2627 |
2628 } // namespace internal | 2628 } // namespace internal |
2629 } // namespace v8 | 2629 } // namespace v8 |
2630 #endif // V8_TARGET_ARCH_S390 | 2630 #endif // V8_TARGET_ARCH_S390 |
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