Simplified CPU/CpuFeatures a bit.

src/arm64/cpu-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 31 matching lines @@
 #endif
 unsigned CpuFeatures::supported_ = 0;
 unsigned CpuFeatures::found_by_runtime_probing_only_ = 0;
 unsigned CpuFeatures::cross_compile_ = 0;
 
 // Initialise to smallest possible cache size.
 unsigned CpuFeatures::dcache_line_size_ = 1;
 unsigned CpuFeatures::icache_line_size_ = 1;
 
 
-void CPU::SetUp() {
-  CpuFeatures::Probe();
-}
-
-
-bool CPU::SupportsCrankshaft() {
-  return true;
-}
-
-
 void CPU::FlushICache(void* address, size_t length) {
   if (length == 0) {
     return;
   }
 
 #ifdef USE_SIMULATOR
   // TODO(all): consider doing some cache simulation to ensure every address
   // run has been synced.
   USE(address);
   USE(length);
@@ skipping 60 matching lines @@
       [isize] "r"  (isize),
       [end]   "r"  (end)
     // This code does not write to memory but without the dependency gcc might
     // move this code before the code is generated.
     : "cc", "memory"
   );  // NOLINT
 #endif
 }
 
 
-void CpuFeatures::Probe() {
+void CpuFeatures::Probe(bool serializer_enabled) {
   // Compute I and D cache line size. The cache type register holds
   // information about the caches.
   uint32_t cache_type_register = GetCacheType();
 
   static const int kDCacheLineSizeShift = 16;
   static const int kICacheLineSizeShift = 0;
   static const uint32_t kDCacheLineSizeMask = 0xf << kDCacheLineSizeShift;
   static const uint32_t kICacheLineSizeMask = 0xf << kICacheLineSizeShift;
 
   // The cache type register holds the size of the I and D caches as a power of
@@ skipping 37 matching lines @@
   // Copy the content of the cache type register to a core register.
   __asm__ __volatile__ ("mrs %[ctr], ctr_el0"  // NOLINT
                         : [ctr] "=r" (cache_type_register));
   return cache_type_register;
 #endif
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64