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Unified Diff: src/s390/assembler-s390.h

Issue 2589063002: s390: clean up RR/RRE/RRD/RIL format in Assembler (Closed)
Patch Set: remove comments Created 4 years ago
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Index: src/s390/assembler-s390.h
diff --git a/src/s390/assembler-s390.h b/src/s390/assembler-s390.h
index 501535faa99cf0cade2035ebe885a3acd9b6cfa3..e121906b0e81ee9a2d398b4fdb1eaeb17e426aae 100644
--- a/src/s390/assembler-s390.h
+++ b/src/s390/assembler-s390.h
@@ -545,6 +545,163 @@ class Assembler : public AssemblerBase {
// ---------------------------------------------------------------------------
// Code generation
+ template <class T, int size, int lo, int hi>
+ inline T getfield(T value) {
+ DCHECK(lo < hi);
+ DCHECK(size > 0);
+ int mask = hi - lo;
+ int shift = size * 8 - hi;
+ uint32_t mask_value = (mask == 32) ? 0xffffffff : (1 << mask) - 1;
+ return (value & mask_value) << shift;
+ }
+
+ // Declare generic instruction formats by fields
+ inline void e_format(Opcode opcode) {
+ emit2bytes(getfield<uint16_t, 2, 0, 16>(opcode));
+ }
+
+ inline void i_format(Opcode opcode, int f1) {
+ emit2bytes(getfield<uint16_t, 2, 0, 8>(opcode) |
+ getfield<uint16_t, 2, 8, 16>(f1));
+ }
+
+ inline void ie_format(Opcode opcode, int f1, int f2) {
+ emit4bytes(getfield<uint32_t, 4, 0, 16>(opcode) |
+ getfield<uint32_t, 4, 24, 28>(f1) |
+ getfield<uint32_t, 4, 28, 32>(f2));
+ }
+ inline void mii_format(Opcode opcode, int f1, int f2, int f3) {
+ emit6bytes(
+ getfield<uint64_t, 6, 0, 8>(opcode) | getfield<uint64_t, 6, 8, 12>(f1) |
+ getfield<uint64_t, 6, 12, 24>(f2) | getfield<uint64_t, 6, 24, 48>(f3));
+ }
+
+ inline void ri_format(Opcode opcode, int f1, int f2) {
+ uint32_t op1 = opcode >> 4;
+ uint32_t op2 = opcode & 0xf;
+ emit4bytes(
+ getfield<uint32_t, 4, 0, 8>(op1) | getfield<uint32_t, 4, 8, 12>(f1) |
+ getfield<uint32_t, 4, 12, 16>(op2) | getfield<uint32_t, 4, 16, 32>(f2));
+ }
+
+ inline void rie_1_format(Opcode opcode, int f1, int f2, int f3, int f4) {
+ uint32_t op1 = opcode >> 8;
+ uint32_t op2 = opcode & 0xff;
+ emit6bytes(
+ getfield<uint64_t, 6, 0, 8>(op1) | getfield<uint64_t, 6, 8, 12>(f1) |
+ getfield<uint64_t, 6, 12, 16>(f2) | getfield<uint64_t, 6, 16, 32>(f3) |
+ getfield<uint64_t, 6, 32, 36>(f4) | getfield<uint64_t, 6, 40, 48>(op2));
+ }
+
+ inline void rie_2_format(Opcode opcode, int f1, int f2, int f3, int f4) {
+ uint32_t op1 = opcode >> 8;
+ uint32_t op2 = opcode & 0xff;
+ emit6bytes(
+ getfield<uint64_t, 6, 0, 8>(op1) | getfield<uint64_t, 6, 8, 12>(f1) |
+ getfield<uint64_t, 6, 12, 16>(f2) | getfield<uint64_t, 6, 16, 32>(f3) |
+ getfield<uint64_t, 6, 32, 40>(f4) | getfield<uint64_t, 6, 40, 48>(op2));
+ }
+
+ inline void rie_3_format(Opcode opcode, int f1, int f2, int f3, int f4,
+ int f5) {
+ uint32_t op1 = opcode >> 8;
+ uint32_t op2 = opcode & 0xff;
+ emit6bytes(
+ getfield<uint64_t, 6, 0, 8>(op1) | getfield<uint64_t, 6, 8, 12>(f1) |
+ getfield<uint64_t, 6, 12, 16>(f2) | getfield<uint64_t, 6, 16, 24>(f3) |
+ getfield<uint64_t, 6, 24, 32>(f4) | getfield<uint64_t, 6, 32, 40>(f5) |
+ getfield<uint64_t, 6, 40, 48>(op2));
+ }
+
+#define DECLARE_S390_RIL_AB_INSTRUCTIONS(name, op_name, op_value) \
+ template <class R1> \
+ inline void name(R1 r1, const Operand& i2) { \
+ ril_format(op_name, r1.code(), i2.immediate()); \
+ }
+#define DECLARE_S390_RIL_C_INSTRUCTIONS(name, op_name, op_value) \
+ inline void name(Condition m1, const Operand& i2) { \
+ ril_format(op_name, m1, i2.immediate()); \
+ }
+
+ inline void ril_format(Opcode opcode, int f1, int f2) {
+ uint32_t op1 = opcode >> 4;
+ uint32_t op2 = opcode & 0xf;
+ emit6bytes(
+ getfield<uint64_t, 6, 0, 8>(op1) | getfield<uint64_t, 6, 8, 12>(f1) |
+ getfield<uint64_t, 6, 12, 16>(op2) | getfield<uint64_t, 6, 16, 48>(f2));
+ }
+ S390_RIL_A_OPCODE_LIST(DECLARE_S390_RIL_AB_INSTRUCTIONS)
+ S390_RIL_B_OPCODE_LIST(DECLARE_S390_RIL_AB_INSTRUCTIONS)
+ S390_RIL_C_OPCODE_LIST(DECLARE_S390_RIL_C_INSTRUCTIONS)
+#undef DECLARE_S390_RIL_AB_INSTRUCTIONS
+#undef DECLARE_S390_RIL_C_INSTRUCTIONS
+
+ inline void ris_format(Opcode opcode, int f1, int f2, int f3, int f4,
+ int f5) {
+ uint32_t op1 = opcode >> 8;
+ uint32_t op2 = opcode & 0xff;
+ emit6bytes(
+ getfield<uint64_t, 6, 0, 8>(op1) | getfield<uint64_t, 6, 8, 12>(f1) |
+ getfield<uint64_t, 6, 12, 16>(f2) | getfield<uint64_t, 6, 16, 20>(f3) |
+ getfield<uint64_t, 6, 20, 32>(f4) | getfield<uint64_t, 6, 32, 40>(f5) |
+ getfield<uint64_t, 6, 40, 48>(op2));
+ }
+
+#define DECLARE_S390_RR_INSTRUCTIONS(name, op_name, op_value) \
+ inline void name(Register r1, Register r2) { \
+ rr_format(op_name, r1.code(), r2.code()); \
+ } \
+ inline void name(DoubleRegister r1, DoubleRegister r2) { \
+ rr_format(op_name, r1.code(), r2.code()); \
+ } \
+ inline void name(Condition m1, Register r2) { \
+ rr_format(op_name, m1, r2.code()); \
+ }
+
+ inline void rr_format(Opcode opcode, int f1, int f2) {
+ emit2bytes(getfield<uint16_t, 2, 0, 8>(opcode) |
+ getfield<uint16_t, 2, 8, 12>(f1) |
+ getfield<uint16_t, 2, 12, 16>(f2));
+ }
+ S390_RR_OPCODE_LIST(DECLARE_S390_RR_INSTRUCTIONS)
+#undef DECLARE_S390_RR_INSTRUCTIONS
+
+#define DECLARE_S390_RRD_INSTRUCTIONS(name, op_name, op_value) \
+ template <class R1, class R2, class R3> \
+ inline void name(R1 r1, R3 r3, R2 r2) { \
+ rrd_format(op_name, r1.code(), r3.code(), r2.code()); \
+ }
+ inline void rrd_format(Opcode opcode, int f1, int f2, int f3) {
+ emit4bytes(getfield<uint32_t, 4, 0, 16>(opcode) |
+ getfield<uint32_t, 4, 16, 20>(f1) |
+ getfield<uint32_t, 4, 24, 28>(f2) |
+ getfield<uint32_t, 4, 28, 32>(f3));
+ }
+ S390_RRD_OPCODE_LIST(DECLARE_S390_RRD_INSTRUCTIONS)
+#undef DECLARE_S390_RRD_INSTRUCTIONS
+
+#define DECLARE_S390_RRE_INSTRUCTIONS(name, op_name, op_value) \
+ template <class R1, class R2> \
+ inline void name(R1 r1, R2 r2) { \
+ rre_format(op_name, r1.code(), r2.code()); \
+ }
+ inline void rre_format(Opcode opcode, int f1, int f2) {
+ emit4bytes(getfield<uint32_t, 4, 0, 16>(opcode) |
+ getfield<uint32_t, 4, 24, 28>(f1) |
+ getfield<uint32_t, 4, 28, 32>(f2));
+ }
+ S390_RRE_OPCODE_LIST(DECLARE_S390_RRE_INSTRUCTIONS)
+ // Special format
+ void lzdr(DoubleRegister r1) { rre_format(LZDR, r1.code(), 0); }
+#undef DECLARE_S390_RRE_INSTRUCTIONS
+
+ inline void rrf_format(Opcode opcode, int f1, int f2, int f3, int f4) {
+ emit4bytes(
+ getfield<uint32_t, 4, 0, 16>(opcode) |
+ getfield<uint32_t, 4, 16, 20>(f1) | getfield<uint32_t, 4, 20, 24>(f2) |
+ getfield<uint32_t, 4, 24, 28>(f3) | getfield<uint32_t, 4, 28, 32>(f4));
+ }
+
// Helper for unconditional branch to Label with update to save register
void b(Register r, Label* l) {
int32_t halfwords = branch_offset(l) / 2;
@@ -647,10 +804,6 @@ class Assembler : public AssemblerBase {
void name(Register r1, Register r2, const Operand& i3, const Operand& i4, \
const Operand& i5)
-#define RIL1_FORM(name) void name(Register r1, const Operand& i2)
-
-#define RIL2_FORM(name) void name(Condition m1, const Operand& i2)
-
#define RXE_FORM(name) \
void name(Register r1, const MemOperand& opnd); \
void name(Register r1, Register b2, Register x2, Disp d2)
@@ -679,8 +832,6 @@ class Assembler : public AssemblerBase {
void name(Register b1, Disp d1, const Operand& i2); \
void name(const MemOperand& opnd, const Operand& i2)
-#define RRE_FORM(name) void name(Register r1, Register r2)
-
#define RRF1_FORM(name) void name(Register r1, Register r2, Register r3)
#define RRF2_FORM(name) void name(Condition m1, Register r1, Register r2)
@@ -712,8 +863,6 @@ class Assembler : public AssemblerBase {
void name(Register r1, Condition m3, Register b2, Disp d2); \
void name(Register r1, Condition m3, const MemOperand& opnd)
-#define RRD_FORM(name) void name(Register r1, Register r3, Register r2)
-
#define RRS_FORM(name) \
void name(Register r1, Register r2, Register b4, Disp d4, Condition m3); \
void name(Register r1, Register r2, Condition m3, const MemOperand& opnd)
@@ -809,62 +958,37 @@ class Assembler : public AssemblerBase {
// S390 instruction sets
RX_FORM(bc);
- RR_FORM(bctr);
RX_FORM(cd);
- RRE_FORM(cdr);
RXE_FORM(cdb);
RXE_FORM(ceb);
RXE_FORM(ddb);
- RRE_FORM(ddbr);
SS1_FORM(ed);
- RRE_FORM(epair);
RX_FORM(ex);
RRF2_FORM(fidbr);
- RRE_FORM(flogr);
RX_FORM(ic_z);
RXY_FORM(icy);
- RIL1_FORM(iihf);
RI1_FORM(iihh);
RI1_FORM(iihl);
- RIL1_FORM(iilf);
- RIL1_FORM(lgfi);
RI1_FORM(iilh);
RI1_FORM(iill);
- RRE_FORM(lcgr);
- RR_FORM(lcr);
RX_FORM(le_z);
RXY_FORM(ley);
- RIL1_FORM(llihf);
- RIL1_FORM(llilf);
- RRE_FORM(lngr);
- RR_FORM(lnr);
RSY1_FORM(loc);
RXY_FORM(lrv);
- RRE_FORM(lrvr);
- RRE_FORM(lrvgr);
RXY_FORM(lrvh);
RXY_FORM(lrvg);
RXE_FORM(mdb);
- RRE_FORM(mdbr);
SS4_FORM(mvck);
SSF_FORM(mvcos);
SS4_FORM(mvcs);
SS1_FORM(mvn);
SS1_FORM(nc);
SI_FORM(ni);
- RIL1_FORM(nihf);
- RIL1_FORM(nilf);
RI1_FORM(nilh);
RI1_FORM(nill);
- RIL1_FORM(oihf);
- RIL1_FORM(oilf);
RI1_FORM(oill);
- RRE_FORM(popcnt);
RXE_FORM(sdb);
- RRE_FORM(sdbr);
- RIL1_FORM(slfi);
RXY_FORM(slgf);
- RIL1_FORM(slgfi);
RS1_FORM(srdl);
RX_FORM(ste);
RXY_FORM(stey);
@@ -874,51 +998,35 @@ class Assembler : public AssemblerBase {
RI1_FORM(tmll);
SS1_FORM(tr);
S_FORM(ts);
- RIL1_FORM(xihf);
- RIL1_FORM(xilf);
// Load Address Instructions
void la(Register r, const MemOperand& opnd);
void lay(Register r, const MemOperand& opnd);
- void larl(Register r1, const Operand& opnd);
void larl(Register r, Label* l);
// Load Instructions
void lb(Register r, const MemOperand& src);
- void lbr(Register r1, Register r2);
void lgb(Register r, const MemOperand& src);
- void lgbr(Register r1, Register r2);
void lh(Register r, const MemOperand& src);
void lhy(Register r, const MemOperand& src);
- void lhr(Register r1, Register r2);
void lgh(Register r, const MemOperand& src);
- void lghr(Register r1, Register r2);
void l(Register r, const MemOperand& src);
void ly(Register r, const MemOperand& src);
- void lr(Register r1, Register r2);
void lg(Register r, const MemOperand& src);
- void lgr(Register r1, Register r2);
void lgf(Register r, const MemOperand& src);
- void lgfr(Register r1, Register r2);
void lhi(Register r, const Operand& imm);
void lghi(Register r, const Operand& imm);
// Load And Test Instructions
void lt_z(Register r, const MemOperand& src);
void ltg(Register r, const MemOperand& src);
- void ltr(Register r1, Register r2);
- void ltgr(Register r1, Register r2);
- void ltgfr(Register r1, Register r2);
// Load Logical Instructions
void llc(Register r, const MemOperand& src);
void llgc(Register r, const MemOperand& src);
void llgf(Register r, const MemOperand& src);
- void llgfr(Register r1, Register r2);
void llh(Register r, const MemOperand& src);
void llgh(Register r, const MemOperand& src);
- void llhr(Register r1, Register r2);
- void llghr(Register r1, Register r2);
// Load Multiple Instructions
void lm(Register r1, Register r2, const MemOperand& src);
@@ -948,24 +1056,16 @@ class Assembler : public AssemblerBase {
// Compare Instructions
void c(Register r, const MemOperand& opnd);
void cy(Register r, const MemOperand& opnd);
- void cr_z(Register r1, Register r2);
void cg(Register r, const MemOperand& opnd);
- void cgr(Register r1, Register r2);
void ch(Register r, const MemOperand& opnd);
void chy(Register r, const MemOperand& opnd);
void chi(Register r, const Operand& opnd);
void cghi(Register r, const Operand& opnd);
- void cfi(Register r, const Operand& opnd);
- void cgfi(Register r, const Operand& opnd);
// Compare Logical Instructions
void cl(Register r, const MemOperand& opnd);
void cly(Register r, const MemOperand& opnd);
- void clr(Register r1, Register r2);
void clg(Register r, const MemOperand& opnd);
- void clgr(Register r1, Register r2);
- void clfi(Register r, const Operand& opnd);
- void clgfi(Register r, const Operand& opnd);
void cli(const MemOperand& mem, const Operand& imm);
void cliy(const MemOperand& mem, const Operand& imm);
void clc(const MemOperand& opnd1, const MemOperand& opnd2, Length length);
@@ -1027,52 +1127,38 @@ class Assembler : public AssemblerBase {
void mvc(const MemOperand& opnd1, const MemOperand& opnd2, uint32_t length);
// Branch Instructions
- void basr(Register r1, Register r2);
- void bcr(Condition m, Register target);
void bct(Register r, const MemOperand& opnd);
void bctg(Register r, const MemOperand& opnd);
void bras(Register r, const Operand& opnd);
- void brasl(Register r, const Operand& opnd);
void brc(Condition c, const Operand& opnd);
- void brcl(Condition m, const Operand& opnd, bool isCodeTarget = false);
void brct(Register r1, const Operand& opnd);
void brctg(Register r1, const Operand& opnd);
// 32-bit Add Instructions
void a(Register r1, const MemOperand& opnd);
void ay(Register r1, const MemOperand& opnd);
- void afi(Register r1, const Operand& opnd);
void ah(Register r1, const MemOperand& opnd);
void ahy(Register r1, const MemOperand& opnd);
void ahi(Register r1, const Operand& opnd);
void ahik(Register r1, Register r3, const Operand& opnd);
- void ar(Register r1, Register r2);
void ark(Register r1, Register r2, Register r3);
void asi(const MemOperand&, const Operand&);
// 64-bit Add Instructions
void ag(Register r1, const MemOperand& opnd);
void agf(Register r1, const MemOperand& opnd);
- void agfi(Register r1, const Operand& opnd);
- void agfr(Register r1, Register r2);
void aghi(Register r1, const Operand& opnd);
void aghik(Register r1, Register r3, const Operand& opnd);
- void agr(Register r1, Register r2);
void agrk(Register r1, Register r2, Register r3);
void agsi(const MemOperand&, const Operand&);
// 32-bit Add Logical Instructions
void al_z(Register r1, const MemOperand& opnd);
void aly(Register r1, const MemOperand& opnd);
- void alfi(Register r1, const Operand& opnd);
- void alr(Register r1, Register r2);
- void alcr(Register r1, Register r2);
void alrk(Register r1, Register r2, Register r3);
// 64-bit Add Logical Instructions
void alg(Register r1, const MemOperand& opnd);
- void algfi(Register r1, const Operand& opnd);
- void algr(Register r1, Register r2);
void algrk(Register r1, Register r2, Register r3);
// 32-bit Subtract Instructions
@@ -1080,107 +1166,69 @@ class Assembler : public AssemblerBase {
void sy(Register r1, const MemOperand& opnd);
void sh(Register r1, const MemOperand& opnd);
void shy(Register r1, const MemOperand& opnd);
- void sr(Register r1, Register r2);
void srk(Register r1, Register r2, Register r3);
// 64-bit Subtract Instructions
void sg(Register r1, const MemOperand& opnd);
void sgf(Register r1, const MemOperand& opnd);
- void sgr(Register r1, Register r2);
- void sgfr(Register r1, Register r2);
void sgrk(Register r1, Register r2, Register r3);
// 32-bit Subtract Logical Instructions
void sl(Register r1, const MemOperand& opnd);
void sly(Register r1, const MemOperand& opnd);
- void slr(Register r1, Register r2);
void slrk(Register r1, Register r2, Register r3);
- void slbr(Register r1, Register r2);
// 64-bit Subtract Logical Instructions
void slg(Register r1, const MemOperand& opnd);
- void slgr(Register r1, Register r2);
void slgrk(Register r1, Register r2, Register r3);
// 32-bit Multiply Instructions
void m(Register r1, const MemOperand& opnd);
void mfy(Register r1, const MemOperand& opnd);
- void mr_z(Register r1, Register r2);
void ml(Register r1, const MemOperand& opnd);
- void mlr(Register r1, Register r2);
void ms(Register r1, const MemOperand& opnd);
void msy(Register r1, const MemOperand& opnd);
- void msfi(Register r1, const Operand& opnd);
- void msr(Register r1, Register r2);
void mh(Register r1, const MemOperand& opnd);
void mhy(Register r1, const MemOperand& opnd);
void mhi(Register r1, const Operand& opnd);
// 64-bit Multiply Instructions
void mlg(Register r1, const MemOperand& opnd);
- void mlgr(Register r1, Register r2);
void mghi(Register r1, const Operand& opnd);
- void msgfi(Register r1, const Operand& opnd);
void msg(Register r1, const MemOperand& opnd);
- void msgr(Register r1, Register r2);
// 32-bit Divide Instructions
void d(Register r1, const MemOperand& opnd);
- void dr(Register r1, Register r2);
void dl(Register r1, const MemOperand& opnd);
- void dlr(Register r1, Register r2);
-
- // 64-bit Divide Instructions
- void dlgr(Register r1, Register r2);
- void dsgr(Register r1, Register r2);
// Bitwise Instructions (AND / OR / XOR)
void n(Register r1, const MemOperand& opnd);
void ny(Register r1, const MemOperand& opnd);
- void nr(Register r1, Register r2);
void nrk(Register r1, Register r2, Register r3);
void ng(Register r1, const MemOperand& opnd);
- void ngr(Register r1, Register r2);
void ngrk(Register r1, Register r2, Register r3);
void o(Register r1, const MemOperand& opnd);
void oy(Register r1, const MemOperand& opnd);
- void or_z(Register r1, Register r2);
void ork(Register r1, Register r2, Register r3);
void og(Register r1, const MemOperand& opnd);
- void ogr(Register r1, Register r2);
void ogrk(Register r1, Register r2, Register r3);
void x(Register r1, const MemOperand& opnd);
void xy(Register r1, const MemOperand& opnd);
- void xr(Register r1, Register r2);
void xrk(Register r1, Register r2, Register r3);
void xg(Register r1, const MemOperand& opnd);
- void xgr(Register r1, Register r2);
void xgrk(Register r1, Register r2, Register r3);
void xc(const MemOperand& opnd1, const MemOperand& opnd2, Length length);
- // Bitwise GPR <-> FPR Conversion Instructions
- void lgdr(Register r1, DoubleRegister f2);
- void ldgr(DoubleRegister f1, Register r2);
-
// Floating Point Load / Store Instructions
void ld(DoubleRegister r1, const MemOperand& opnd);
void ldy(DoubleRegister r1, const MemOperand& opnd);
void le_z(DoubleRegister r1, const MemOperand& opnd);
void ley(DoubleRegister r1, const MemOperand& opnd);
- void ldr(DoubleRegister r1, DoubleRegister r2);
- void ltdbr(DoubleRegister r1, DoubleRegister r2);
- void ltebr(DoubleRegister r1, DoubleRegister r2);
void std(DoubleRegister r1, const MemOperand& opnd);
void stdy(DoubleRegister r1, const MemOperand& opnd);
void ste(DoubleRegister r1, const MemOperand& opnd);
void stey(DoubleRegister r1, const MemOperand& opnd);
- // Floating Point Load Rounded/Positive Instructions
- void ledbr(DoubleRegister r1, DoubleRegister r2);
- void ldebr(DoubleRegister r1, DoubleRegister r2);
- void lpebr(DoubleRegister r1, DoubleRegister r2);
- void lpdbr(DoubleRegister r1, DoubleRegister r2);
-
// Floating <-> Fixed Point Conversion Instructions
void cdlfbr(Condition m3, Condition m4, DoubleRegister fltReg,
Register fixReg);
@@ -1199,40 +1247,20 @@ class Assembler : public AssemblerBase {
void clgebr(Condition m3, Condition m4, Register fixReg,
DoubleRegister fltReg);
void cfdbr(Condition m, Register fixReg, DoubleRegister fltReg);
- void cdfbr(DoubleRegister fltReg, Register fixReg);
void cgebr(Condition m, Register fixReg, DoubleRegister fltReg);
void cgdbr(Condition m, Register fixReg, DoubleRegister fltReg);
- void cegbr(DoubleRegister fltReg, Register fixReg);
- void cdgbr(DoubleRegister fltReg, Register fixReg);
void cfebr(Condition m3, Register fixReg, DoubleRegister fltReg);
void cefbr(Condition m3, DoubleRegister fltReg, Register fixReg);
// Floating Point Compare Instructions
- void cebr(DoubleRegister r1, DoubleRegister r2);
void cdb(DoubleRegister r1, const MemOperand& opnd);
- void cdbr(DoubleRegister r1, DoubleRegister r2);
// Floating Point Arithmetic Instructions
- void aebr(DoubleRegister r1, DoubleRegister r2);
void adb(DoubleRegister r1, const MemOperand& opnd);
- void adbr(DoubleRegister r1, DoubleRegister r2);
- void lzdr(DoubleRegister r1);
- void sebr(DoubleRegister r1, DoubleRegister r2);
void sdb(DoubleRegister r1, const MemOperand& opnd);
- void sdbr(DoubleRegister r1, DoubleRegister r2);
- void meebr(DoubleRegister r1, DoubleRegister r2);
void mdb(DoubleRegister r1, const MemOperand& opnd);
- void mdbr(DoubleRegister r1, DoubleRegister r2);
- void debr(DoubleRegister r1, DoubleRegister r2);
void ddb(DoubleRegister r1, const MemOperand& opnd);
- void ddbr(DoubleRegister r1, DoubleRegister r2);
- void madbr(DoubleRegister r1, DoubleRegister r2, DoubleRegister r3);
- void msdbr(DoubleRegister r1, DoubleRegister r2, DoubleRegister r3);
- void sqebr(DoubleRegister r1, DoubleRegister r2);
void sqdb(DoubleRegister r1, const MemOperand& opnd);
- void sqdbr(DoubleRegister r1, DoubleRegister r2);
- void lcdbr(DoubleRegister r1, DoubleRegister r2);
- void lcebr(DoubleRegister r1, DoubleRegister r2);
void ldeb(DoubleRegister r1, const MemOperand& opnd);
enum FIDBRA_MASK3 {
@@ -1415,9 +1443,6 @@ class Assembler : public AssemblerBase {
// Helpers to emit binary encoding for various instruction formats.
- inline void rr_form(Opcode op, Register r1, Register r2);
- inline void rr_form(Opcode op, DoubleRegister r1, DoubleRegister r2);
- inline void rr_form(Opcode op, Condition m1, Register r2);
inline void rr2_form(uint8_t op, Condition m1, Register r2);
inline void rx_form(Opcode op, Register r1, Register x2, Register b2,
@@ -1432,17 +1457,9 @@ class Assembler : public AssemblerBase {
inline void rie_f_form(Opcode op, Register r1, Register r2, const Operand& i3,
const Operand& i4, const Operand& i5);
- inline void ril_form(Opcode op, Register r1, const Operand& i2);
- inline void ril_form(Opcode op, Condition m1, const Operand& i2);
-
inline void ris_form(Opcode op, Register r1, Condition m3, Register b4,
Disp d4, const Operand& i2);
- inline void rrd_form(Opcode op, Register r1, Register r3, Register r2);
-
- inline void rre_form(Opcode op, Register r1, Register r2);
- inline void rre_form(Opcode op, DoubleRegister r1, DoubleRegister r2);
-
inline void rrf1_form(Opcode op, Register r1, Register r2, Register r3);
inline void rrf1_form(uint32_t x);
inline void rrf2_form(uint32_t x);
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