| OLD | NEW |
| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
| (...skipping 752 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 763 Condition m3) { \ | 763 Condition m3) { \ |
| 764 uint64_t code = (static_cast<uint64_t>(opcode_value & 0xFF00)) * B32 | \ | 764 uint64_t code = (static_cast<uint64_t>(opcode_value & 0xFF00)) * B32 | \ |
| 765 (static_cast<uint64_t>(v1.code())) * B36 | \ | 765 (static_cast<uint64_t>(v1.code())) * B36 | \ |
| 766 (static_cast<uint64_t>(v2.code())) * B32 | \ | 766 (static_cast<uint64_t>(v2.code())) * B32 | \ |
| 767 (static_cast<uint64_t>(m5 & 0xF)) * B20 | \ | 767 (static_cast<uint64_t>(m5 & 0xF)) * B20 | \ |
| 768 (static_cast<uint64_t>(m4 & 0xF)) * B16 | \ | 768 (static_cast<uint64_t>(m4 & 0xF)) * B16 | \ |
| 769 (static_cast<uint64_t>(m3 & 0xF)) * B12 | \ | 769 (static_cast<uint64_t>(m3 & 0xF)) * B12 | \ |
| 770 (static_cast<uint64_t>(opcode_value & 0x00FF)); \ | 770 (static_cast<uint64_t>(opcode_value & 0x00FF)); \ |
| 771 emit6bytes(code); \ | 771 emit6bytes(code); \ |
| 772 } | 772 } |
| 773 VRR_A_OPCODE_LIST(DECLARE_VRR_A_INSTRUCTIONS) | 773 S390_VRR_A_OPCODE_LIST(DECLARE_VRR_A_INSTRUCTIONS) |
| 774 #undef DECLARE_VRR_A_INSTRUCTIONS | 774 #undef DECLARE_VRR_A_INSTRUCTIONS |
| 775 | 775 |
| 776 #define DECLARE_VRR_C_INSTRUCTIONS(name, opcode_name, opcode_value) \ | 776 #define DECLARE_VRR_C_INSTRUCTIONS(name, opcode_name, opcode_value) \ |
| 777 void name(DoubleRegister v1, DoubleRegister v2, DoubleRegister v3, \ | 777 void name(DoubleRegister v1, DoubleRegister v2, DoubleRegister v3, \ |
| 778 Condition m6, Condition m5, Condition m4) { \ | 778 Condition m6, Condition m5, Condition m4) { \ |
| 779 uint64_t code = (static_cast<uint64_t>(opcode_value & 0xFF00)) * B32 | \ | 779 uint64_t code = (static_cast<uint64_t>(opcode_value & 0xFF00)) * B32 | \ |
| 780 (static_cast<uint64_t>(v1.code())) * B36 | \ | 780 (static_cast<uint64_t>(v1.code())) * B36 | \ |
| 781 (static_cast<uint64_t>(v2.code())) * B32 | \ | 781 (static_cast<uint64_t>(v2.code())) * B32 | \ |
| 782 (static_cast<uint64_t>(v3.code())) * B28 | \ | 782 (static_cast<uint64_t>(v3.code())) * B28 | \ |
| 783 (static_cast<uint64_t>(m6 & 0xF)) * B20 | \ | 783 (static_cast<uint64_t>(m6 & 0xF)) * B20 | \ |
| 784 (static_cast<uint64_t>(m5 & 0xF)) * B16 | \ | 784 (static_cast<uint64_t>(m5 & 0xF)) * B16 | \ |
| 785 (static_cast<uint64_t>(m4 & 0xF)) * B12 | \ | 785 (static_cast<uint64_t>(m4 & 0xF)) * B12 | \ |
| 786 (static_cast<uint64_t>(opcode_value & 0x00FF)); \ | 786 (static_cast<uint64_t>(opcode_value & 0x00FF)); \ |
| 787 emit6bytes(code); \ | 787 emit6bytes(code); \ |
| 788 } | 788 } |
| 789 VRR_C_OPCODE_LIST(DECLARE_VRR_C_INSTRUCTIONS) | 789 S390_VRR_C_OPCODE_LIST(DECLARE_VRR_C_INSTRUCTIONS) |
| 790 #undef DECLARE_VRR_C_INSTRUCTIONS | 790 #undef DECLARE_VRR_C_INSTRUCTIONS |
| 791 | 791 |
| 792 // Single Element format | 792 // Single Element format |
| 793 void vfa(DoubleRegister v1, DoubleRegister v2, DoubleRegister v3) { | 793 void vfa(DoubleRegister v1, DoubleRegister v2, DoubleRegister v3) { |
| 794 vfa(v1, v2, v3, static_cast<Condition>(0), static_cast<Condition>(8), | 794 vfa(v1, v2, v3, static_cast<Condition>(0), static_cast<Condition>(8), |
| 795 static_cast<Condition>(3)); | 795 static_cast<Condition>(3)); |
| 796 } | 796 } |
| 797 void vfs(DoubleRegister v1, DoubleRegister v2, DoubleRegister v3) { | 797 void vfs(DoubleRegister v1, DoubleRegister v2, DoubleRegister v3) { |
| 798 vfs(v1, v2, v3, static_cast<Condition>(0), static_cast<Condition>(8), | 798 vfs(v1, v2, v3, static_cast<Condition>(0), static_cast<Condition>(8), |
| 799 static_cast<Condition>(3)); | 799 static_cast<Condition>(3)); |
| (...skipping 714 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1514 | 1514 |
| 1515 class EnsureSpace BASE_EMBEDDED { | 1515 class EnsureSpace BASE_EMBEDDED { |
| 1516 public: | 1516 public: |
| 1517 explicit EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); } | 1517 explicit EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); } |
| 1518 }; | 1518 }; |
| 1519 | 1519 |
| 1520 } // namespace internal | 1520 } // namespace internal |
| 1521 } // namespace v8 | 1521 } // namespace v8 |
| 1522 | 1522 |
| 1523 #endif // V8_S390_ASSEMBLER_S390_H_ | 1523 #endif // V8_S390_ASSEMBLER_S390_H_ |
| OLD | NEW |