[Turbofan] Add native ARM support for basic SIMD 32x4 operations.

src/arm/simulator-arm.cc

Index: src/arm/simulator-arm.cc
diff --git a/src/arm/simulator-arm.cc b/src/arm/simulator-arm.cc
index 12654834f2877b53738ea63170819206375050ad..b31d855715935a14e987157c5d7a678bea01398d 100644
--- a/src/arm/simulator-arm.cc
+++ b/src/arm/simulator-arm.cc
@@ -3360,12 +3360,13 @@ void Simulator::DecodeTypeVFP(Instruction* instr) {
       int vn = instr->VFPNRegValue(kDoublePrecision);
       int rt = instr->RtValue();
       int opc1_opc2 = (instr->Bits(22, 21) << 2) | instr->Bits(6, 5);
+      uint64_t data;
+      get_d_register(vn, &data);
       if ((opc1_opc2 & 0xb) == 0) {
         // NeonS32 / NeonU32
-        double dn_value = get_double_from_d_register(vn);
-        int32_t data[2];
-        memcpy(data, &dn_value, 8);
-        set_register(rt, data[instr->Bit(21)]);
+        int32_t int_data[2];
+        memcpy(int_data, &data, sizeof(int_data));
+        set_register(rt, int_data[instr->Bit(21)]);
       } else {
         uint64_t data;
         get_d_register(vn, &data);
@@ -4129,12 +4130,12 @@ void Simulator::DecodeSpecialCondition(Instruction* instr) {
               break;
             case 2:
               // s32 <- f32, round to zero.
-              q_data[i] = static_cast<uint32_t>(
+              q_data[i] = bit_cast<uint32_t>(
                   ConvertDoubleToInt(bit_cast<float>(q_data[i]), false, RZ));
               break;
             case 3:
               // u32 <- f32, round to zero.
-              q_data[i] = static_cast<uint32_t>(
+              q_data[i] = bit_cast<uint32_t>(
                   ConvertDoubleToInt(bit_cast<float>(q_data[i]), true, RZ));
               break;
           }