[Turbofan] Add native ARM support for basic SIMD 32x4 operations.

src/compiler/arm/instruction-codes-arm.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 101 matching lines @@
   V(ArmFloat64SilenceNaN)          \
   V(ArmLdrb)                       \
   V(ArmLdrsb)                      \
   V(ArmStrb)                       \
   V(ArmLdrh)                       \
   V(ArmLdrsh)                      \
   V(ArmStrh)                       \
   V(ArmLdr)                        \
   V(ArmStr)                        \
   V(ArmPush)                       \
-  V(ArmPoke)
+  V(ArmPoke)                       \
+  V(ArmFloat32x4Splat)             \
+  V(ArmFloat32x4ExtractLane)       \
+  V(ArmFloat32x4ReplaceLane)       \
+  V(ArmFloat32x4FromInt32x4)       \
+  V(ArmFloat32x4FromUint32x4)      \
+  V(ArmFloat32x4Add)               \
+  V(ArmFloat32x4Sub)               \
+  V(ArmInt32x4Splat)               \
+  V(ArmInt32x4ExtractLane)         \
+  V(ArmInt32x4ReplaceLane)         \
+  V(ArmInt32x4FromFloat32x4)       \
+  V(ArmUint32x4FromFloat32x4)      \
+  V(ArmInt32x4Add)                 \
+  V(ArmInt32x4Sub)                 \
+  V(ArmInt32x4Eq)                  \
+  V(ArmInt32x4Ne)                  \
+  V(ArmSimd32x4Select)
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
 #define TARGET_ADDRESSING_MODE_LIST(V)  \
   V(Offset_RI)        /* [%r0 + K] */   \
   V(Offset_RR)        /* [%r0 + %r1] */ \
   V(Operand2_I)       /* K */           \
   V(Operand2_R)       /* %r0 */         \
   V(Operand2_R_ASR_I) /* %r0 ASR K */   \
   V(Operand2_R_LSL_I) /* %r0 LSL K */   \
   V(Operand2_R_LSR_I) /* %r0 LSR K */   \
   V(Operand2_R_ROR_I) /* %r0 ROR K */   \
   V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
   V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
   V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
   V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_