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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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112 V(ArmFloat64SilenceNaN) \ | 112 V(ArmFloat64SilenceNaN) \ |
113 V(ArmLdrb) \ | 113 V(ArmLdrb) \ |
114 V(ArmLdrsb) \ | 114 V(ArmLdrsb) \ |
115 V(ArmStrb) \ | 115 V(ArmStrb) \ |
116 V(ArmLdrh) \ | 116 V(ArmLdrh) \ |
117 V(ArmLdrsh) \ | 117 V(ArmLdrsh) \ |
118 V(ArmStrh) \ | 118 V(ArmStrh) \ |
119 V(ArmLdr) \ | 119 V(ArmLdr) \ |
120 V(ArmStr) \ | 120 V(ArmStr) \ |
121 V(ArmPush) \ | 121 V(ArmPush) \ |
122 V(ArmPoke) | 122 V(ArmPoke) \ |
| 123 V(ArmFloat32x4Splat) \ |
| 124 V(ArmFloat32x4ExtractLane) \ |
| 125 V(ArmFloat32x4ReplaceLane) \ |
| 126 V(ArmFloat32x4FromInt32x4) \ |
| 127 V(ArmFloat32x4FromUint32x4) \ |
| 128 V(ArmFloat32x4Add) \ |
| 129 V(ArmFloat32x4Sub) \ |
| 130 V(ArmInt32x4Splat) \ |
| 131 V(ArmInt32x4ExtractLane) \ |
| 132 V(ArmInt32x4ReplaceLane) \ |
| 133 V(ArmInt32x4FromFloat32x4) \ |
| 134 V(ArmUint32x4FromFloat32x4) \ |
| 135 V(ArmInt32x4Add) \ |
| 136 V(ArmInt32x4Sub) \ |
| 137 V(ArmInt32x4Eq) \ |
| 138 V(ArmInt32x4Ne) \ |
| 139 V(ArmSimd32x4Select) |
123 | 140 |
124 // Addressing modes represent the "shape" of inputs to an instruction. | 141 // Addressing modes represent the "shape" of inputs to an instruction. |
125 // Many instructions support multiple addressing modes. Addressing modes | 142 // Many instructions support multiple addressing modes. Addressing modes |
126 // are encoded into the InstructionCode of the instruction and tell the | 143 // are encoded into the InstructionCode of the instruction and tell the |
127 // code generator after register allocation which assembler method to call. | 144 // code generator after register allocation which assembler method to call. |
128 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 145 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
129 V(Offset_RI) /* [%r0 + K] */ \ | 146 V(Offset_RI) /* [%r0 + K] */ \ |
130 V(Offset_RR) /* [%r0 + %r1] */ \ | 147 V(Offset_RR) /* [%r0 + %r1] */ \ |
131 V(Operand2_I) /* K */ \ | 148 V(Operand2_I) /* K */ \ |
132 V(Operand2_R) /* %r0 */ \ | 149 V(Operand2_R) /* %r0 */ \ |
133 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ | 150 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ |
134 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ | 151 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ |
135 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ | 152 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ |
136 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ | 153 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ |
137 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ | 154 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ |
138 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ | 155 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ |
139 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ | 156 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ |
140 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ | 157 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ |
141 | 158 |
142 } // namespace compiler | 159 } // namespace compiler |
143 } // namespace internal | 160 } // namespace internal |
144 } // namespace v8 | 161 } // namespace v8 |
145 | 162 |
146 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 163 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
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