[Turbofan] Add native ARM support for basic SIMD 32x4 operations.

src/arm/simulator-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_ARM
 
@@ skipping 3342 matching lines @@
             UNREACHABLE();
             break;
         }
         set_q_register(vd, q_data);
       }
     } else if ((instr->VLValue() == 0x1) && (instr->VCValue() == 0x1)) {
       // vmov (scalar to ARM core register)
       int vn = instr->VFPNRegValue(kDoublePrecision);
       int rt = instr->RtValue();
       int opc1_opc2 = (instr->Bits(22, 21) << 2) | instr->Bits(6, 5);
+      uint64_t data;
+      get_d_register(vn, &data);
       if ((opc1_opc2 & 0xb) == 0) {
         // NeonS32 / NeonU32
-        double dn_value = get_double_from_d_register(vn);
-        int32_t data[2];
-        memcpy(data, &dn_value, 8);

[bbudge, 2016/12/16 22:24:29]

Not sure why, but this doesn't work correctly sometimes.

-        set_register(rt, data[instr->Bit(21)]);
+        int32_t int_data[2];
+        memcpy(int_data, &data, sizeof(int_data));
+        set_register(rt, int_data[instr->Bit(21)]);
       } else {
         uint64_t data;
         get_d_register(vn, &data);
         bool u = instr->Bit(23) != 0;
         if ((opc1_opc2 & 0x8) != 0) {
           // NeonS8 / NeonU8
           int i = opc1_opc2 & 0x7;
           int shift = i * kBitsPerByte;
           uint32_t scalar = (data >> shift) & 0xFFu;
           if (!u && (scalar & 0x80) != 0) scalar |= 0xffffff00;
@@ skipping 743 matching lines @@
               q_data[i] = bit_cast<uint32_t>(
                   std::round(static_cast<float>(bit_cast<int32_t>(q_data[i]))));
               break;
             case 1:
               // f32 <- u32, round towards nearest.
               q_data[i] =
                   bit_cast<uint32_t>(std::round(static_cast<float>(q_data[i])));
               break;
             case 2:
               // s32 <- f32, round to zero.
-              q_data[i] = static_cast<uint32_t>(

[bbudge, 2016/12/16 22:24:29]

I missed these, but I think the behavior is undefined in some cases. Also below.

+              q_data[i] = bit_cast<uint32_t>(

[Rodolph Perfetta, 2016/12/19 13:43:00]

static_cast int32_t -> uint32_t is well defined. bitcast will work too
obviously.

[bbudge, 2016/12/20 00:57:13]

I googled a little  and when values are outside the target type range, behavior
is "implementation defined" so I decided to be safe here and switch to bit_cast.

http://stackoverflow.com/questions/13150449/efficient-unsigned-to-signed-cast....

                   ConvertDoubleToInt(bit_cast<float>(q_data[i]), false, RZ));
               break;
             case 3:
               // u32 <- f32, round to zero.
-              q_data[i] = static_cast<uint32_t>(
+              q_data[i] = bit_cast<uint32_t>(

[Rodolph Perfetta, 2016/12/19 13:43:00]

ditto.

                   ConvertDoubleToInt(bit_cast<float>(q_data[i]), true, RZ));
               break;
           }
         }
         set_q_register(Vd, q_data);
       } else if ((instr->Bits(21, 16) == 0x32) && (instr->Bits(11, 7) == 0) &&
                  (instr->Bit(4) == 0)) {
         if (instr->Bit(6) == 0) {
           // vswp Dd, Dm.
           uint64_t dval, mval;
@@ skipping 569 matching lines @@
   set_register(sp, current_sp + sizeof(uintptr_t));
   return address;
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_ARM