OLD | NEW |
1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/base/adapters.h" | 5 #include "src/base/adapters.h" |
6 #include "src/base/bits.h" | 6 #include "src/base/bits.h" |
7 #include "src/compiler/instruction-selector-impl.h" | 7 #include "src/compiler/instruction-selector-impl.h" |
8 #include "src/compiler/node-matchers.h" | 8 #include "src/compiler/node-matchers.h" |
9 #include "src/compiler/node-properties.h" | 9 #include "src/compiler/node-properties.h" |
10 | 10 |
(...skipping 2268 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2279 AddressingMode addressing_mode = kMode_Offset_RR; | 2279 AddressingMode addressing_mode = kMode_Offset_RR; |
2280 InstructionOperand inputs[4]; | 2280 InstructionOperand inputs[4]; |
2281 size_t input_count = 0; | 2281 size_t input_count = 0; |
2282 inputs[input_count++] = g.UseUniqueRegister(base); | 2282 inputs[input_count++] = g.UseUniqueRegister(base); |
2283 inputs[input_count++] = g.UseUniqueRegister(index); | 2283 inputs[input_count++] = g.UseUniqueRegister(index); |
2284 inputs[input_count++] = g.UseUniqueRegister(value); | 2284 inputs[input_count++] = g.UseUniqueRegister(value); |
2285 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); | 2285 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); |
2286 Emit(code, 0, nullptr, input_count, inputs); | 2286 Emit(code, 0, nullptr, input_count, inputs); |
2287 } | 2287 } |
2288 | 2288 |
| 2289 void InstructionSelector::VisitCreateFloat32x4(Node* node) { |
| 2290 ArmOperandGenerator g(this); |
| 2291 Emit(kArmFloat32x4Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0))); |
| 2292 } |
| 2293 |
| 2294 void InstructionSelector::VisitFloat32x4ExtractLane(Node* node) { |
| 2295 ArmOperandGenerator g(this); |
| 2296 int32_t lane = OpParameter<int32_t>(node); |
| 2297 Emit(kArmFloat32x4ExtractLane, g.DefineAsRegister(node), |
| 2298 g.UseRegister(node->InputAt(0)), g.UseImmediate(lane)); |
| 2299 } |
| 2300 |
| 2301 void InstructionSelector::VisitFloat32x4ReplaceLane(Node* node) { |
| 2302 ArmOperandGenerator g(this); |
| 2303 int32_t lane = OpParameter<int32_t>(node); |
| 2304 Emit(kArmFloat32x4ReplaceLane, g.DefineAsRegister(node), |
| 2305 g.UseRegister(node->InputAt(0)), g.UseImmediate(lane), |
| 2306 g.Use(node->InputAt(1))); |
| 2307 } |
| 2308 |
| 2309 void InstructionSelector::VisitFloat32x4FromInt32x4(Node* node) { |
| 2310 ArmOperandGenerator g(this); |
| 2311 Emit(kArmFloat32x4FromInt32x4, g.DefineAsRegister(node), |
| 2312 g.UseRegister(node->InputAt(0))); |
| 2313 } |
| 2314 |
| 2315 void InstructionSelector::VisitFloat32x4FromUint32x4(Node* node) { |
| 2316 ArmOperandGenerator g(this); |
| 2317 Emit(kArmFloat32x4FromUint32x4, g.DefineAsRegister(node), |
| 2318 g.UseRegister(node->InputAt(0))); |
| 2319 } |
| 2320 |
| 2321 void InstructionSelector::VisitFloat32x4Add(Node* node) { |
| 2322 ArmOperandGenerator g(this); |
| 2323 Emit(kArmFloat32x4Add, g.DefineAsRegister(node), |
| 2324 g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); |
| 2325 } |
| 2326 |
| 2327 void InstructionSelector::VisitFloat32x4Sub(Node* node) { |
| 2328 ArmOperandGenerator g(this); |
| 2329 Emit(kArmFloat32x4Sub, g.DefineAsRegister(node), |
| 2330 g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); |
| 2331 } |
| 2332 |
| 2333 void InstructionSelector::VisitCreateInt32x4(Node* node) { |
| 2334 ArmOperandGenerator g(this); |
| 2335 Emit(kArmInt32x4Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0))); |
| 2336 } |
| 2337 |
| 2338 void InstructionSelector::VisitInt32x4ExtractLane(Node* node) { |
| 2339 ArmOperandGenerator g(this); |
| 2340 int32_t lane = OpParameter<int32_t>(node); |
| 2341 Emit(kArmInt32x4ExtractLane, g.DefineAsRegister(node), |
| 2342 g.UseRegister(node->InputAt(0)), g.UseImmediate(lane)); |
| 2343 } |
| 2344 |
| 2345 void InstructionSelector::VisitInt32x4ReplaceLane(Node* node) { |
| 2346 ArmOperandGenerator g(this); |
| 2347 int32_t lane = OpParameter<int32_t>(node); |
| 2348 Emit(kArmInt32x4ReplaceLane, g.DefineAsRegister(node), |
| 2349 g.UseRegister(node->InputAt(0)), g.UseImmediate(lane), |
| 2350 g.Use(node->InputAt(1))); |
| 2351 } |
| 2352 |
| 2353 void InstructionSelector::VisitInt32x4FromFloat32x4(Node* node) { |
| 2354 ArmOperandGenerator g(this); |
| 2355 Emit(kArmInt32x4FromFloat32x4, g.DefineAsRegister(node), |
| 2356 g.UseRegister(node->InputAt(0))); |
| 2357 } |
| 2358 |
| 2359 void InstructionSelector::VisitUint32x4FromFloat32x4(Node* node) { |
| 2360 ArmOperandGenerator g(this); |
| 2361 Emit(kArmUint32x4FromFloat32x4, g.DefineAsRegister(node), |
| 2362 g.UseRegister(node->InputAt(0))); |
| 2363 } |
| 2364 |
| 2365 void InstructionSelector::VisitInt32x4Add(Node* node) { |
| 2366 ArmOperandGenerator g(this); |
| 2367 Emit(kArmInt32x4Add, g.DefineAsRegister(node), |
| 2368 g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); |
| 2369 } |
| 2370 |
| 2371 void InstructionSelector::VisitInt32x4Sub(Node* node) { |
| 2372 ArmOperandGenerator g(this); |
| 2373 Emit(kArmInt32x4Sub, g.DefineAsRegister(node), |
| 2374 g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); |
| 2375 } |
| 2376 |
| 2377 void InstructionSelector::VisitInt32x4Equal(Node* node) { |
| 2378 ArmOperandGenerator g(this); |
| 2379 Emit(kArmInt32x4Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)), |
| 2380 g.UseRegister(node->InputAt(1))); |
| 2381 } |
| 2382 |
| 2383 void InstructionSelector::VisitInt32x4NotEqual(Node* node) { |
| 2384 ArmOperandGenerator g(this); |
| 2385 Emit(kArmInt32x4Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)), |
| 2386 g.UseRegister(node->InputAt(1))); |
| 2387 } |
| 2388 |
| 2389 void InstructionSelector::VisitSimd32x4Select(Node* node) { |
| 2390 ArmOperandGenerator g(this); |
| 2391 Emit(kArmSimd32x4Select, g.DefineAsRegister(node), |
| 2392 g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), |
| 2393 g.UseRegister(node->InputAt(2))); |
| 2394 } |
| 2395 |
2289 // static | 2396 // static |
2290 MachineOperatorBuilder::Flags | 2397 MachineOperatorBuilder::Flags |
2291 InstructionSelector::SupportedMachineOperatorFlags() { | 2398 InstructionSelector::SupportedMachineOperatorFlags() { |
2292 MachineOperatorBuilder::Flags flags; | 2399 MachineOperatorBuilder::Flags flags; |
2293 if (CpuFeatures::IsSupported(SUDIV)) { | 2400 if (CpuFeatures::IsSupported(SUDIV)) { |
2294 // The sdiv and udiv instructions correctly return 0 if the divisor is 0, | 2401 // The sdiv and udiv instructions correctly return 0 if the divisor is 0, |
2295 // but the fall-back implementation does not. | 2402 // but the fall-back implementation does not. |
2296 flags |= MachineOperatorBuilder::kInt32DivIsSafe | | 2403 flags |= MachineOperatorBuilder::kInt32DivIsSafe | |
2297 MachineOperatorBuilder::kUint32DivIsSafe; | 2404 MachineOperatorBuilder::kUint32DivIsSafe; |
2298 } | 2405 } |
(...skipping 20 matching lines...) Expand all Loading... |
2319 Vector<MachineType> req_aligned = Vector<MachineType>::New(2); | 2426 Vector<MachineType> req_aligned = Vector<MachineType>::New(2); |
2320 req_aligned[0] = MachineType::Float32(); | 2427 req_aligned[0] = MachineType::Float32(); |
2321 req_aligned[1] = MachineType::Float64(); | 2428 req_aligned[1] = MachineType::Float64(); |
2322 return MachineOperatorBuilder::AlignmentRequirements:: | 2429 return MachineOperatorBuilder::AlignmentRequirements:: |
2323 SomeUnalignedAccessUnsupported(req_aligned, req_aligned); | 2430 SomeUnalignedAccessUnsupported(req_aligned, req_aligned); |
2324 } | 2431 } |
2325 | 2432 |
2326 } // namespace compiler | 2433 } // namespace compiler |
2327 } // namespace internal | 2434 } // namespace internal |
2328 } // namespace v8 | 2435 } // namespace v8 |
OLD | NEW |