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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1048 // Print the Instruction bits. | 1048 // Print the Instruction bits. |
1049 out_buffer_pos_ += | 1049 out_buffer_pos_ += |
1050 SNPrintF(out_buffer_ + out_buffer_pos_, "%012" PRIx64 " ", | 1050 SNPrintF(out_buffer_ + out_buffer_pos_, "%012" PRIx64 " ", |
1051 instr->InstructionBits<SixByteInstr>()); | 1051 instr->InstructionBits<SixByteInstr>()); |
1052 | 1052 |
1053 Opcode opcode = instr->S390OpcodeValue(); | 1053 Opcode opcode = instr->S390OpcodeValue(); |
1054 switch (opcode) { | 1054 switch (opcode) { |
1055 case DUMY: | 1055 case DUMY: |
1056 Format(instr, "dumy\t'r1, 'd2 ( 'r2d, 'r3 )"); | 1056 Format(instr, "dumy\t'r1, 'd2 ( 'r2d, 'r3 )"); |
1057 break; | 1057 break; |
| 1058 #define DECODE_VRR_C_INSTRUCTIONS(name, opcode_name, opcode_value) \ |
| 1059 case opcode_name: \ |
| 1060 Format(instr, #name "\t'f1,'f2,'f3"); \ |
| 1061 break; |
| 1062 VRR_A_OPCODE_LIST(DECODE_VRR_C_INSTRUCTIONS) |
| 1063 #undef DECODE_VRR_C_INSTRUCTIONS |
1058 case LLILF: | 1064 case LLILF: |
1059 Format(instr, "llilf\t'r1,'i7"); | 1065 Format(instr, "llilf\t'r1,'i7"); |
1060 break; | 1066 break; |
1061 case LLIHF: | 1067 case LLIHF: |
1062 Format(instr, "llihf\t'r1,'i7"); | 1068 Format(instr, "llihf\t'r1,'i7"); |
1063 break; | 1069 break; |
1064 case AFI: | 1070 case AFI: |
1065 Format(instr, "afi\t'r1,'i7"); | 1071 Format(instr, "afi\t'r1,'i7"); |
1066 break; | 1072 break; |
1067 case ASI: | 1073 case ASI: |
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1477 byte* prev_pc = pc; | 1483 byte* prev_pc = pc; |
1478 pc += d.InstructionDecode(buffer, pc); | 1484 pc += d.InstructionDecode(buffer, pc); |
1479 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), | 1485 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), |
1480 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1486 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1481 } | 1487 } |
1482 } | 1488 } |
1483 | 1489 |
1484 } // namespace disasm | 1490 } // namespace disasm |
1485 | 1491 |
1486 #endif // V8_TARGET_ARCH_S390 | 1492 #endif // V8_TARGET_ARCH_S390 |
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