Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(3)

Side by Side Diff: src/s390/constants-s390.h

Issue 2582683002: s390x: implement vector support on s390 (Closed)
Patch Set: fix comments and dchecks Created 4 years ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/s390/assembler-s390.cc ('k') | src/s390/disasm-s390.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_S390_CONSTANTS_S390_H_ 5 #ifndef V8_S390_CONSTANTS_S390_H_
6 #define V8_S390_CONSTANTS_S390_H_ 6 #define V8_S390_CONSTANTS_S390_H_
7 7
8 // Get the standard printf format macros for C99 stdint types. 8 // Get the standard printf format macros for C99 stdint types.
9 #ifndef __STDC_FORMAT_MACROS 9 #ifndef __STDC_FORMAT_MACROS
10 #define __STDC_FORMAT_MACROS 10 #define __STDC_FORMAT_MACROS
(...skipping 139 matching lines...) Expand 10 before | Expand all | Expand 10 after
150 150
151 // Instr is merely used by the Assembler to distinguish 32bit integers 151 // Instr is merely used by the Assembler to distinguish 32bit integers
152 // representing instructions from usual 32 bit values. 152 // representing instructions from usual 32 bit values.
153 // Instruction objects are pointers to 32bit values, and provide methods to 153 // Instruction objects are pointers to 32bit values, and provide methods to
154 // access the various ISA fields. 154 // access the various ISA fields.
155 typedef int32_t Instr; 155 typedef int32_t Instr;
156 typedef uint16_t TwoByteInstr; 156 typedef uint16_t TwoByteInstr;
157 typedef uint32_t FourByteInstr; 157 typedef uint32_t FourByteInstr;
158 typedef uint64_t SixByteInstr; 158 typedef uint64_t SixByteInstr;
159 159
160 #define VRR_A_OPCODE_LIST(V) \
161 V(wfc, WFC, 0xE7CB) /* VECTOR FP COMPARE SCALAR */ \
162 V(vcdg, VCDG, 0xE7D3) /* VECTOR FP CONVERT FROM FIXED 64-BIT */ \
163 V(vcdlg, VCDLG, 0xE7C1) /* VECTOR FP CONVERT FROM LOGICAL 64-BIT */ \
164 V(vcgd, VCGD, 0xE7C2) /* VECTOR FP CONVERT TO FIXED 64-BIT */ \
165 V(vclgd, VCLGD, 0xE7C0) /* VECTOR FP CONVERT TO LOGICAL 64-BIT */ \
166 V(vfi, VFI, 0xE7C7) /* VECTOR LOAD FP INTEGER */ \
167 V(vlde, VLDE, 0xE7C4) /* VECTOR FP LOAD LENGTHENED */ \
168 V(vled, VLED, 0xE7C5) /* VECTOR FP LOAD ROUNDED */ \
169 V(vfpso, VFPSO, 0xE7CC) /* VECTOR FP PERFORM SIGN OPERATION */ \
170 V(vfsq, VFSQ, 0xE7CE) /* VECTOR FP SQUARE ROOT */ \
171 V(wfk, WFK, 0xE7CA) /* VECTOR FP COMPARE AND SIGNAL SCALAR */
172
173 #define VRR_C_OPCODE_LIST(V) \
174 V(vfa, VFA, 0xE7E3) /* VECTOR FP ADD */ \
175 V(vfs, VFS, 0xE7E2) /* VECTOR FP SUBTRACT */ \
176 V(vfm, VFM, 0xE7E7) /* VECTOR FP MULTIPLY */ \
177 V(vfd, VFD, 0xE7E5) /* VECTOR FP DIVIDE */
178
160 // Opcodes as defined in Appendix B-2 table 179 // Opcodes as defined in Appendix B-2 table
161 enum Opcode { 180 enum Opcode {
162 A = 0x5A, // Add (32) 181 #define DECLARE_OPCODES(name, opcode_name, opcode_value) \
182 opcode_name = opcode_value,
183 VRR_A_OPCODE_LIST(DECLARE_OPCODES) VRR_C_OPCODE_LIST(DECLARE_OPCODES)
184 #undef DECLARE_OPCODES
185
186 A = 0x5A, // Add (32)
163 ADB = 0xED1A, // Add (long BFP) 187 ADB = 0xED1A, // Add (long BFP)
164 ADBR = 0xB31A, // Add (long BFP) 188 ADBR = 0xB31A, // Add (long BFP)
165 ADTR = 0xB3D2, // Add (long DFP) 189 ADTR = 0xB3D2, // Add (long DFP)
166 ADTRA = 0xB3D2, // Add (long DFP) 190 ADTRA = 0xB3D2, // Add (long DFP)
167 AEB = 0xED0A, // Add (short BFP) 191 AEB = 0xED0A, // Add (short BFP)
168 AEBR = 0xB30A, // Add (short BFP) 192 AEBR = 0xB30A, // Add (short BFP)
169 AFI = 0xC29, // Add Immediate (32) 193 AFI = 0xC29, // Add Immediate (32)
170 AG = 0xE308, // Add (64) 194 AG = 0xE308, // Add (64)
171 AGF = 0xE318, // Add (64<-32) 195 AGF = 0xE318, // Add (64<-32)
172 AGFI = 0xC28, // Add Immediate (64<-32) 196 AGFI = 0xC28, // Add Immediate (64<-32)
(...skipping 1124 matching lines...) Expand 10 before | Expand all | Expand 10 after
1297 // Use the At(pc) function to create references to Instruction. 1321 // Use the At(pc) function to create references to Instruction.
1298 static Instruction* At(byte* pc) { 1322 static Instruction* At(byte* pc) {
1299 return reinterpret_cast<Instruction*>(pc); 1323 return reinterpret_cast<Instruction*>(pc);
1300 } 1324 }
1301 1325
1302 private: 1326 private:
1303 // We need to prevent the creation of instances of class Instruction. 1327 // We need to prevent the creation of instances of class Instruction.
1304 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 1328 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
1305 }; 1329 };
1306 1330
1331 #define DECLARE_FIELD_FOR_SIX_BYTE_INSTR(name, T, lo, hi) \
1332 inline int name() const { \
1333 return Bits<SixByteInstr, T>(47 - (lo), 47 - (hi) + 1); \
1334 }
1335
1336 // VRR Instruction
1337 class VRR_C_Instruction : Instruction {
1338 public:
1339 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R1Value, int, 8, 12);
1340 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R2Value, int, 12, 16);
1341 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(R3Value, int, 16, 20);
1342 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M6Value, uint32_t, 24, 28);
1343 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M5Value, uint32_t, 28, 32);
1344 DECLARE_FIELD_FOR_SIX_BYTE_INSTR(M4Value, uint32_t, 32, 36);
1345 inline int size() const { return 6; }
1346 };
1347
1307 // I Instruction -- suspect this will not be used, 1348 // I Instruction -- suspect this will not be used,
1308 // but implement for completeness 1349 // but implement for completeness
1309 class IInstruction : Instruction { 1350 class IInstruction : Instruction {
1310 public: 1351 public:
1311 inline int IValue() const { return Bits<TwoByteInstr, int>(7, 0); } 1352 inline int IValue() const { return Bits<TwoByteInstr, int>(7, 0); }
1312 1353
1313 inline int size() const { return 2; } 1354 inline int size() const { return 2; }
1314 }; 1355 };
1315 1356
1316 // RR Instruction 1357 // RR Instruction
(...skipping 206 matching lines...) Expand 10 before | Expand all | Expand 10 after
1523 static int Number(const char* name); 1564 static int Number(const char* name);
1524 1565
1525 private: 1566 private:
1526 static const char* names_[kNumDoubleRegisters]; 1567 static const char* names_[kNumDoubleRegisters];
1527 }; 1568 };
1528 1569
1529 } // namespace internal 1570 } // namespace internal
1530 } // namespace v8 1571 } // namespace v8
1531 1572
1532 #endif // V8_S390_CONSTANTS_S390_H_ 1573 #endif // V8_S390_CONSTANTS_S390_H_
OLDNEW
« no previous file with comments | « src/s390/assembler-s390.cc ('k') | src/s390/disasm-s390.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698