[ARM] Add NEON instructions for implementing SIMD.

src/arm/assembler-arm.h

Index: src/arm/assembler-arm.h
diff --git a/src/arm/assembler-arm.h b/src/arm/assembler-arm.h
index 235d80be8386489cdc79b84fd509577c24d28e6a..c33ca17bf1fe5a6b650c40a60525d7220a01845e 100644
--- a/src/arm/assembler-arm.h
+++ b/src/arm/assembler-arm.h
@@ -1362,6 +1362,10 @@ class Assembler : public AssemblerBase {
   void vcvt_s32_f32(const QwNeonRegister dst, const QwNeonRegister src);
   void vcvt_u32_f32(const QwNeonRegister dst, const QwNeonRegister src);
 
+  void vabs(const QwNeonRegister dst, const QwNeonRegister src);
+  void vabs(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
+  void vneg(const QwNeonRegister dst, const QwNeonRegister src);
+  void vneg(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
   void veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2);
   void veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
   void vadd(const QwNeonRegister dst, const QwNeonRegister src1,
@@ -1372,12 +1376,21 @@ class Assembler : public AssemblerBase {
             const QwNeonRegister src2);
   void vsub(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
+  void vmul(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2);
+  void vmul(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2);
   void vtst(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
   void vceq(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
   void vbsl(const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
+  void vext(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2, int bytes);
+  void vzip(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
+  void vrev(NeonSize op_size, NeonSize element_size, const QwNeonRegister dst,

[Rodolph Perfetta (ARM), 2016/12/16 20:50:11]

would you consider having 3 instructions here:
 * vrev16
 * vrev32
 * vrev64
This would match the ARM documentation and mirror the integer instructions
(rev16, etc). This would also make the parameters passed more in line with other
neon instructions (first parameter is the element size).

What do you think?

[bbudge, 2016/12/17 01:08:32]

I think it's a good idea. Done.

+            const QwNeonRegister src);
   void vtbl(const DwVfpRegister dst, const NeonListOperand& list,
             const DwVfpRegister index);
   void vtbx(const DwVfpRegister dst, const NeonListOperand& list,