[ARM] Add NEON instructions for implementing SIMD.

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 983 matching lines @@
       COMPARE(vdup(q15, s2),
               "f3f4ec41       vdup q15, d1[0]");
       COMPARE(vcvt_f32_s32(q15, q1),
               "f3fbe642       vcvt.f32.s32 q15, q1");
       COMPARE(vcvt_f32_u32(q8, q9),
               "f3fb06e2       vcvt.f32.u32 q8, q9");
       COMPARE(vcvt_s32_f32(q15, q1),
               "f3fbe742       vcvt.s32.f32 q15, q1");
       COMPARE(vcvt_u32_f32(q8, q9),
               "f3fb07e2       vcvt.u32.f32 q8, q9");
+      COMPARE(vabs(q0, q1),
+              "f3b90742       vabs.f32 q0, q1");
+      COMPARE(vabs(Neon8, q6, q7),
+              "f3b1c34e       vabs.s8 q6, q7");
+      COMPARE(vabs(Neon16, q0, q1),
+              "f3b50342       vabs.s16 q0, q1");
+      COMPARE(vabs(Neon32, q0, q1),
+              "f3b90342       vabs.s32 q0, q1");
+      COMPARE(vneg(q0, q1),
+              "f3b907c2       vneg.f32 q0, q1");
+      COMPARE(vneg(Neon8, q6, q7),
+              "f3b1c3ce       vneg.s8 q6, q7");
+      COMPARE(vneg(Neon16, q0, q1),
+              "f3b503c2       vneg.s16 q0, q1");
+      COMPARE(vneg(Neon32, q0, q1),
+              "f3b903c2       vneg.s32 q0, q1");
       COMPARE(veor(d0, d1, d2),
               "f3010112       veor d0, d1, d2");
       COMPARE(veor(d0, d30, d31),
               "f30e01bf       veor d0, d30, d31");
       COMPARE(veor(q0, q1, q2),
               "f3020154       veor q0, q1, q2");
       COMPARE(veor(q15, q0, q8),
               "f340e170       veor q15, q0, q8");
       COMPARE(vadd(q15, q0, q8),
               "f240ed60       vadd.f32 q15, q0, q8");
       COMPARE(vadd(Neon8, q0, q1, q2),
               "f2020844       vadd.i8 q0, q1, q2");
       COMPARE(vadd(Neon16, q1, q2, q8),
               "f2142860       vadd.i16 q1, q2, q8");
       COMPARE(vadd(Neon32, q15, q0, q8),
               "f260e860       vadd.i32 q15, q0, q8");
       COMPARE(vsub(q15, q0, q8),
               "f260ed60       vsub.f32 q15, q0, q8");
       COMPARE(vsub(Neon8, q0, q1, q2),
               "f3020844       vsub.i8 q0, q1, q2");
       COMPARE(vsub(Neon16, q1, q2, q8),
               "f3142860       vsub.i16 q1, q2, q8");
       COMPARE(vsub(Neon32, q15, q0, q8),
               "f360e860       vsub.i32 q15, q0, q8");
+      COMPARE(vmul(q0, q1, q2),
+              "f3020d54       vmul.f32 q0, q1, q2");
+      COMPARE(vmul(Neon8, q0, q1, q2),
+              "f2020954       vmul.i8 q0, q1, q2");
+      COMPARE(vmul(Neon16, q1, q2, q8),
+              "f2142970       vmul.i16 q1, q2, q8");
+      COMPARE(vmul(Neon32, q15, q0, q8),
+              "f260e970       vmul.i32 q15, q0, q8");
       COMPARE(vtst(Neon8, q0, q1, q2),
               "f2020854       vtst.i8 q0, q1, q2");
       COMPARE(vtst(Neon16, q1, q2, q8),
               "f2142870       vtst.i16 q1, q2, q8");
       COMPARE(vtst(Neon32, q15, q0, q8),
               "f260e870       vtst.i32 q15, q0, q8");
       COMPARE(vceq(Neon8, q0, q1, q2),
               "f3020854       vceq.i8 q0, q1, q2");
       COMPARE(vceq(Neon16, q1, q2, q8),
               "f3142870       vceq.i16 q1, q2, q8");
       COMPARE(vceq(Neon32, q15, q0, q8),
               "f360e870       vceq.i32 q15, q0, q8");
       COMPARE(vbsl(q0, q1, q2),
               "f3120154       vbsl q0, q1, q2");
       COMPARE(vbsl(q15, q0, q8),
               "f350e170       vbsl q15, q0, q8");
+      COMPARE(vext(q15, q0, q8, 3),
+              "f2f0e360       vext.8 q15, q0, q8, #3");
+      COMPARE(vzip(Neon16, q15, q0),
+              "f3f6e1c0       vzip.16 q15, q0");
+      COMPARE(vrev64(Neon8, q15, q0),
+              "f3f0e040       vrev64.8 q15, q0");
       COMPARE(vtbl(d0, NeonListOperand(d1, 1), d2),
               "f3b10802       vtbl.8 d0, {d1}, d2");
       COMPARE(vtbl(d31, NeonListOperand(d0, 2), d4),
               "f3f0f904       vtbl.8 d31, {d0, d1}, d4");
       COMPARE(vtbl(d15, NeonListOperand(d1, 3), d5),
               "f3b1fa05       vtbl.8 d15, {d1, d2, d3}, d5");
       COMPARE(vtbl(d15, NeonListOperand(d1, 4), d5),
               "f3b1fb05       vtbl.8 d15, {d1, d2, d3, d4}, d5");
       COMPARE(vtbx(d0, NeonListOperand(d1, 1), d2),
               "f3b10842       vtbx.8 d0, {d1}, d2");
@@ skipping 286 matching lines @@
 
   COMPARE(ldrexb(r0, r1), "e1d10f9f       ldrexb r0, [r1]");
   COMPARE(strexb(r0, r1, r2), "e1c20f91       strexb r0, r1, [r2]");
   COMPARE(ldrexh(r0, r1), "e1f10f9f       ldrexh r0, [r1]");
   COMPARE(strexh(r0, r1, r2), "e1e20f91       strexh r0, r1, [r2]");
   COMPARE(ldrex(r0, r1), "e1910f9f       ldrex r0, [r1]");
   COMPARE(strex(r0, r1, r2), "e1820f91       strex r0, r1, [r2]");
 
   VERIFY_RUN();
 }