[ARM] Add NEON instructions for implementing SIMD.

src/arm/assembler-arm.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1344 matching lines @@
   void vswp(QwNeonRegister dst, QwNeonRegister src);
   // vdup conditional execution isn't supported.
   void vdup(NeonSize size, const QwNeonRegister dst, const Register src);
   void vdup(const QwNeonRegister dst, const SwVfpRegister src);
 
   void vcvt_f32_s32(const QwNeonRegister dst, const QwNeonRegister src);
   void vcvt_f32_u32(const QwNeonRegister dst, const QwNeonRegister src);
   void vcvt_s32_f32(const QwNeonRegister dst, const QwNeonRegister src);
   void vcvt_u32_f32(const QwNeonRegister dst, const QwNeonRegister src);
 
+  void vabs(const QwNeonRegister dst, const QwNeonRegister src);
+  void vabs(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
+  void vneg(const QwNeonRegister dst, const QwNeonRegister src);
+  void vneg(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
   void veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2);
   void veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
   void vadd(const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
   void vadd(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
   void vsub(const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
   void vsub(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
+  void vmul(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2);
+  void vmul(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2);
   void vtst(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
   void vceq(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
   void vbsl(const QwNeonRegister dst, const QwNeonRegister src1,
             const QwNeonRegister src2);
+  void vext(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2, int bytes);
+  void vzip(NeonSize size, const QwNeonRegister dst, const QwNeonRegister src);
+  void vrev16(NeonSize size, const QwNeonRegister dst,
+            const QwNeonRegister src);
+  void vrev32(NeonSize size, const QwNeonRegister dst,
+            const QwNeonRegister src);
+  void vrev64(NeonSize size, const QwNeonRegister dst,
+            const QwNeonRegister src);
   void vtbl(const DwVfpRegister dst, const NeonListOperand& list,
             const DwVfpRegister index);
   void vtbx(const DwVfpRegister dst, const NeonListOperand& list,
             const DwVfpRegister index);
 
   // Pseudo instructions
 
   // Different nop operations are used by the code generator to detect certain
   // states of the generated code.
   enum NopMarkerTypes {
@@ skipping 389 matching lines @@
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_ASSEMBLER_ARM_H_