ARM64: Use the shifter operand to merge in previous shift instructions.

src/arm64/assembler-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_ASSEMBLER_ARM64_H_
 #define V8_ARM64_ASSEMBLER_ARM64_H_
 
 #include <list>
 #include <map>
 
@@ skipping 1730 matching lines @@
   inline static Instr ImmRotate(unsigned immr, unsigned reg_size);
   inline static Instr ImmLLiteral(int imm19);
   inline static Instr BitN(unsigned bitn, unsigned reg_size);
   inline static Instr ShiftDP(Shift shift);
   inline static Instr ImmDPShift(unsigned amount);
   inline static Instr ExtendMode(Extend extend);
   inline static Instr ImmExtendShift(unsigned left_shift);
   inline static Instr ImmCondCmp(unsigned imm);
   inline static Instr Nzcv(StatusFlags nzcv);
 
+  static bool IsImmAddSub(int64_t immediate);
+  static bool IsImmLogical(uint64_t value,
+                           unsigned width,
+                           unsigned* n,
+                           unsigned* imm_s,
+                           unsigned* imm_r);
+
   // MemOperand offset encoding.
   inline static Instr ImmLSUnsigned(int imm12);
   inline static Instr ImmLS(int imm9);
   inline static Instr ImmLSPair(int imm7, LSDataSize size);
   inline static Instr ImmShiftLS(unsigned shift_amount);
   inline static Instr ImmException(int imm16);
   inline static Instr ImmSystemRegister(int imm15);
   inline static Instr ImmHint(int imm7);
   inline static Instr ImmBarrierDomain(int imm2);
   inline static Instr ImmBarrierType(int imm2);
@@ skipping 93 matching lines @@
   void Logical(const Register& rd,
                const Register& rn,
                const Operand& operand,
                LogicalOp op);
   void LogicalImmediate(const Register& rd,
                         const Register& rn,
                         unsigned n,
                         unsigned imm_s,
                         unsigned imm_r,
                         LogicalOp op);
-  static bool IsImmLogical(uint64_t value,
-                           unsigned width,
-                           unsigned* n,
-                           unsigned* imm_s,
-                           unsigned* imm_r);
 
   void ConditionalCompare(const Register& rn,
                           const Operand& operand,
                           StatusFlags nzcv,
                           Condition cond,
                           ConditionalCompareOp op);
   static bool IsImmConditionalCompare(int64_t immediate);
 
   void AddSubWithCarry(const Register& rd,
                        const Register& rn,
@@ skipping 10 matching lines @@
   void EmitExtendShift(const Register& rd,
                        const Register& rn,
                        Extend extend,
                        unsigned left_shift);
 
   void AddSub(const Register& rd,
               const Register& rn,
               const Operand& operand,
               FlagsUpdate S,
               AddSubOp op);
-  static bool IsImmAddSub(int64_t immediate);
 
   static bool IsImmFP32(float imm);
   static bool IsImmFP64(double imm);
 
   // Find an appropriate LoadStoreOp or LoadStorePairOp for the specified
   // registers. Only simple loads are supported; sign- and zero-extension (such
   // as in LDPSW_x or LDRB_w) are not supported.
   static inline LoadStoreOp LoadOpFor(const CPURegister& rt);
   static inline LoadStorePairOp LoadPairOpFor(const CPURegister& rt,
                                               const CPURegister& rt2);
@@ skipping 315 matching lines @@
 class EnsureSpace BASE_EMBEDDED {
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBufferSpace();
   }
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM64_ASSEMBLER_ARM64_H_