MIPS[64]: Disable fusion multiple-accumulate instructions

src/mips/macro-assembler-mips.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
 
 #include "src/assembler.h"
 #include "src/globals.h"
 #include "src/mips/assembler-mips.h"
@@ skipping 869 matching lines @@
   // the higher 32 bits of the 64-bit coprocessor register,
   // while leaving the low bits unchanged.
   void Mthc1(Register rt, FPURegister fs);
 
   // FP32 mode: move the high part of the double-register pair into
   // general purpose register.
   // FP64 mode: Move the higher 32 bits of the 64-bit coprocessor register into
   // general-purpose register.
   void Mfhc1(Register rt, FPURegister fs);
 
+  void Madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft,
+              FPURegister scratch);
+  void Madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft,
+              FPURegister scratch);
+  void Msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft,
+              FPURegister scratch);
+  void Msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft,
+              FPURegister scratch);
+
   // Wrapper functions for the different cmp/branch types.
   inline void BranchF32(Label* target, Label* nan, Condition cc,
                         FPURegister cmp1, FPURegister cmp2,
                         BranchDelaySlot bd = PROTECT) {
     BranchFCommon(S, target, nan, cc, cmp1, cmp2, bd);
   }
 
   inline void BranchF64(Label* target, Label* nan, Condition cc,
                         FPURegister cmp1, FPURegister cmp2,
                         BranchDelaySlot bd = PROTECT) {
@@ skipping 959 matching lines @@
     dd(GetLabelFunction(index));
   }
 }
 
 #define ACCESS_MASM(masm) masm->
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_