assembler-arm: Use unsigned ints to avoid integer overflow.

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 3893 matching lines @@
 
 void Assembler::vmov(const QwNeonRegister dst, const QwNeonRegister src) {
   DCHECK(IsEnabled(NEON));
   // Instruction details available in ARM DDI 0406C.b, A8-938.
   DCHECK(VfpRegisterIsAvailable(dst));
   DCHECK(VfpRegisterIsAvailable(src));
   int vd, d;
   dst.split_code(&vd, &d);
   int vm, m;
   src.split_code(&vm, &m);
-  emit(0x1E4 * B23 | d * B22 | 2 * B20 | vm * B16 | vd * B12 | B8 | m * B7 |
+  emit(0x1E4U * B23 | d * B22 | 2 * B20 | vm * B16 | vd * B12 | B8 | m * B7 |
        B6 | m * B5 | B4 | vm);
 }
 
 void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) {
   // Instruction details available in ARM DDI 0406C.b, A8.8.418.
   // 1111(31-28) | 00111(27-23) | D(22) | 110010(21-16) |
   // Vd(15-12) | 000000(11-6) | M(5) | 0(4) | Vm(3-0)
   DCHECK(IsEnabled(NEON));
   int vd, d;
   dst.split_code(&vd, &d);
@@ skipping 18 matching lines @@
 void Assembler::veor(DwVfpRegister dst, DwVfpRegister src1,
                      DwVfpRegister src2) {
   // Instruction details available in ARM DDI 0406C.b, A8.8.888.
   DCHECK(IsEnabled(NEON));
   int vd, d;
   dst.split_code(&vd, &d);
   int vn, n;
   src1.split_code(&vn, &n);
   int vm, m;
   src2.split_code(&vm, &m);
-  emit(0x1E6 * B23 | d * B22 | vn * B16 | vd * B12 | B8 | n * B7 | m * B5 | B4 |
-       vm);
+  emit(0x1E6U * B23 | d * B22 | vn * B16 | vd * B12 | B8 | n * B7 | m * B5 |
+       B4 | vm);
 }
 
 void Assembler::veor(QwNeonRegister dst, QwNeonRegister src1,
                      QwNeonRegister src2) {
   // Instruction details available in ARM DDI 0406C.b, A8.8.888.
   DCHECK(IsEnabled(NEON));
   int vd, d;
   dst.split_code(&vd, &d);
   int vn, n;
   src1.split_code(&vn, &n);
   int vm, m;
   src2.split_code(&vm, &m);
-  emit(0x1E6 * B23 | d * B22 | vn * B16 | vd * B12 | B8 | n * B7 | B6 | m * B5 |
-       B4 | vm);
+  emit(0x1E6U * B23 | d * B22 | vn * B16 | vd * B12 | B8 | n * B7 | B6 |
+       m * B5 | B4 | vm);
 }
 
 // Pseudo instructions.
 void Assembler::nop(int type) {
   // ARMv6{K/T2} and v7 have an actual NOP instruction but it serializes
   // some of the CPU's pipeline and has to issue. Older ARM chips simply used
   // MOV Rx, Rx as NOP and it performs better even in newer CPUs.
   // We therefore use MOV Rx, Rx, even on newer CPUs, and use Rx to encode
   // a type.
   DCHECK(0 <= type && type <= 14);  // mov pc, pc isn't a nop.
@@ skipping 535 matching lines @@
     DCHECK(is_uint12(offset));
     instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset));
   }
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM