MIPS[64]: Fix `MIPS: Improve Float(32|64)(Max|Min)`.

src/mips/macro-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
@@ skipping 5861 matching lines @@
   // Check that neither is a smi.
   STATIC_ASSERT(kSmiTag == 0);
   And(scratch1, first, Operand(second));
   JumpIfSmi(scratch1, failure);
   JumpIfNonSmisNotBothSequentialOneByteStrings(first, second, scratch1,
                                                scratch2, failure);
 }
 
 void MacroAssembler::Float32Max(FPURegister dst, FPURegister src1,
                                 FPURegister src2, Label* out_of_line) {
-  DCHECK(!src1.is(src2));
+  if (src1.is(src2)) {
+    Move_s(dst, src1);
+    return;
+  }
 
   // Check if one of operands is NaN.
   BranchF32(nullptr, out_of_line, eq, src1, src2);
 
   if (IsMipsArchVariant(kMips32r6)) {
     max_s(dst, src1, src2);
   } else {
     Label return_left, return_right, done;
 
-    c(OLT, S, src1, src2);
-    bc1t(&return_right);
-    nop();
-
-    c(OLT, S, src2, src1);
-    bc1t(&return_left);
-    nop();
+    BranchF32(&return_right, nullptr, lt, src1, src2);
+    BranchF32(&return_left, nullptr, lt, src2, src1);
 
     // Operands are equal, but check for +/-0.
     mfc1(t8, src1);
-    beq(t8, zero_reg, &return_left);
-    nop();
-    b(&return_right);
-    nop();
+    Branch(&return_left, eq, t8, Operand(zero_reg));
+    Branch(&return_right);
 
     bind(&return_right);
     if (!src2.is(dst)) {
       Move_s(dst, src2);
     }
-    b(&done);
-    nop();
+    Branch(&done);
 
     bind(&return_left);
     if (!src1.is(dst)) {
       Move_s(dst, src1);
     }
 
     bind(&done);
   }
 }
 
 void MacroAssembler::Float32MaxOutOfLine(FPURegister dst, FPURegister src1,
                                          FPURegister src2) {
-  DCHECK(!src1.is(src2));
   add_s(dst, src1, src2);
 }
 
 void MacroAssembler::Float32Min(FPURegister dst, FPURegister src1,
                                 FPURegister src2, Label* out_of_line) {
-  DCHECK(!src1.is(src2));
+  if (src1.is(src2)) {
+    Move_s(dst, src1);
+    return;
+  }
 
   // Check if one of operands is NaN.
   BranchF32(nullptr, out_of_line, eq, src1, src2);
 
   if (IsMipsArchVariant(kMips32r6)) {
     min_s(dst, src1, src2);
   } else {
     Label return_left, return_right, done;
 
-    c(OLT, S, src1, src2);
-    bc1t(&return_left);
-    nop();
-
-    c(OLT, S, src2, src1);
-    bc1t(&return_right);
-    nop();
+    BranchF32(&return_left, nullptr, lt, src1, src2);
+    BranchF32(&return_right, nullptr, lt, src2, src1);
 
     // Left equals right => check for -0.
     mfc1(t8, src1);
-    beq(t8, zero_reg, &return_right);
-    nop();
-    b(&return_left);
-    nop();
+    Branch(&return_right, eq, t8, Operand(zero_reg));
+    Branch(&return_left);
 
     bind(&return_right);
     if (!src2.is(dst)) {
       Move_s(dst, src2);
     }
-    b(&done);
-    nop();
+    Branch(&done);
 
     bind(&return_left);
     if (!src1.is(dst)) {
       Move_s(dst, src1);
     }
 
     bind(&done);
   }
 }
 
 void MacroAssembler::Float32MinOutOfLine(FPURegister dst, FPURegister src1,
                                          FPURegister src2) {
-  DCHECK(!src1.is(src2));
   add_s(dst, src1, src2);
 }
 
 void MacroAssembler::Float64Max(DoubleRegister dst, DoubleRegister src1,
                                 DoubleRegister src2, Label* out_of_line) {
-  DCHECK(!src1.is(src2));
+  if (src1.is(src2)) {
+    Move_d(dst, src1);
+    return;
+  }
 
   // Check if one of operands is NaN.
   BranchF64(nullptr, out_of_line, eq, src1, src2);
 
   if (IsMipsArchVariant(kMips32r6)) {
     max_d(dst, src1, src2);
   } else {
     Label return_left, return_right, done;
 
-    c(OLT, D, src1, src2);
-    bc1t(&return_right);
-    nop();
-
-    c(OLT, D, src2, src1);
-    bc1t(&return_left);
-    nop();
+    BranchF64(&return_right, nullptr, lt, src1, src2);
+    BranchF64(&return_left, nullptr, lt, src2, src1);
 
     // Left equals right => check for -0.
     Mfhc1(t8, src1);
-    beq(t8, zero_reg, &return_left);
-    nop();
-    b(&return_right);
-    nop();
+    Branch(&return_left, eq, t8, Operand(zero_reg));
+    Branch(&return_right);
 
     bind(&return_right);
     if (!src2.is(dst)) {
       Move_d(dst, src2);
     }
-    b(&done);
-    nop();
+    Branch(&done);
 
     bind(&return_left);
     if (!src1.is(dst)) {
       Move_d(dst, src1);
     }
 
     bind(&done);
   }
 }
 
 void MacroAssembler::Float64MaxOutOfLine(DoubleRegister dst,
                                          DoubleRegister src1,
                                          DoubleRegister src2) {
-  DCHECK(!src1.is(src2));
   add_d(dst, src1, src2);
 }
 
 void MacroAssembler::Float64Min(DoubleRegister dst, DoubleRegister src1,
                                 DoubleRegister src2, Label* out_of_line) {
-  DCHECK(!src1.is(src2));
+  if (src1.is(src2)) {
+    Move_d(dst, src1);
+    return;
+  }
 
   // Check if one of operands is NaN.
   BranchF64(nullptr, out_of_line, eq, src1, src2);
 
   if (IsMipsArchVariant(kMips32r6)) {
     min_d(dst, src1, src2);
   } else {
     Label return_left, return_right, done;
 
-    c(OLT, D, src1, src2);
-    bc1t(&return_left);
-    nop();
-
-    c(OLT, D, src2, src1);
-    bc1t(&return_right);
-    nop();
+    BranchF64(&return_left, nullptr, lt, src1, src2);
+    BranchF64(&return_right, nullptr, lt, src2, src1);
 
     // Left equals right => check for -0.
     Mfhc1(t8, src1);
-    beq(t8, zero_reg, &return_right);
-    nop();
-    b(&return_left);
-    nop();
+    Branch(&return_right, eq, t8, Operand(zero_reg));
+    Branch(&return_left);
 
     bind(&return_right);
     if (!src2.is(dst)) {
       Move_d(dst, src2);
     }
-    b(&done);
-    nop();
+    Branch(&done);
 
     bind(&return_left);
     if (!src1.is(dst)) {
       Move_d(dst, src1);
     }
 
     bind(&done);
   }
 }
 
 void MacroAssembler::Float64MinOutOfLine(DoubleRegister dst,
                                          DoubleRegister src1,
                                          DoubleRegister src2) {
-  DCHECK(!src1.is(src2));
   add_d(dst, src1, src2);
 }
 
 void MacroAssembler::JumpIfBothInstanceTypesAreNotSequentialOneByte(
     Register first, Register second, Register scratch1, Register scratch2,
     Label* failure) {
   const int kFlatOneByteStringMask =
       kIsNotStringMask | kStringEncodingMask | kStringRepresentationMask;
   const int kFlatOneByteStringTag =
       kStringTag | kOneByteStringTag | kSeqStringTag;
@@ skipping 541 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS