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1 // Copyright 2014 The Crashpad Authors. All rights reserved. | 1 // Copyright 2014 The Crashpad Authors. All rights reserved. |
2 // | 2 // |
3 // Licensed under the Apache License, Version 2.0 (the "License"); | 3 // Licensed under the Apache License, Version 2.0 (the "License"); |
4 // you may not use this file except in compliance with the License. | 4 // you may not use this file except in compliance with the License. |
5 // You may obtain a copy of the License at | 5 // You may obtain a copy of the License at |
6 // | 6 // |
7 // http://www.apache.org/licenses/LICENSE-2.0 | 7 // http://www.apache.org/licenses/LICENSE-2.0 |
8 // | 8 // |
9 // Unless required by applicable law or agreed to in writing, software | 9 // Unless required by applicable law or agreed to in writing, software |
10 // distributed under the License is distributed on an "AS IS" BASIS, | 10 // distributed under the License is distributed on an "AS IS" BASIS, |
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126 using XMMRegister = CPUContextX86::XMMRegister; | 126 using XMMRegister = CPUContextX86::XMMRegister; |
127 | 127 |
128 struct Fxsave { | 128 struct Fxsave { |
129 uint16_t fcw; // FPU control word | 129 uint16_t fcw; // FPU control word |
130 uint16_t fsw; // FPU status word | 130 uint16_t fsw; // FPU status word |
131 uint8_t ftw; // abridged FPU tag word | 131 uint8_t ftw; // abridged FPU tag word |
132 uint8_t reserved_1; | 132 uint8_t reserved_1; |
133 uint16_t fop; // FPU opcode | 133 uint16_t fop; // FPU opcode |
134 union { | 134 union { |
135 // The expression of these union members is determined by the use of | 135 // The expression of these union members is determined by the use of |
136 // fxsave/fxrstor or fxsave64/fxrstor64 (fxsaveq/fxrstorq). Mac OS X and | 136 // fxsave/fxrstor or fxsave64/fxrstor64 (fxsaveq/fxrstorq). macOS and |
137 // Windows systems use the traditional fxsave/fxrstor structure. | 137 // Windows systems use the traditional fxsave/fxrstor structure. |
138 struct { | 138 struct { |
139 // fxsave/fxrstor | 139 // fxsave/fxrstor |
140 uint32_t fpu_ip; // FPU instruction pointer offset | 140 uint32_t fpu_ip; // FPU instruction pointer offset |
141 uint16_t fpu_cs; // FPU instruction pointer segment selector | 141 uint16_t fpu_cs; // FPU instruction pointer segment selector |
142 uint16_t reserved_2; | 142 uint16_t reserved_2; |
143 uint32_t fpu_dp; // FPU data pointer offset | 143 uint32_t fpu_dp; // FPU data pointer offset |
144 uint16_t fpu_ds; // FPU data pointer segment selector | 144 uint16_t fpu_ds; // FPU data pointer segment selector |
145 uint16_t reserved_3; | 145 uint16_t reserved_3; |
146 }; | 146 }; |
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210 CPUArchitecture architecture; | 210 CPUArchitecture architecture; |
211 union { | 211 union { |
212 CPUContextX86* x86; | 212 CPUContextX86* x86; |
213 CPUContextX86_64* x86_64; | 213 CPUContextX86_64* x86_64; |
214 }; | 214 }; |
215 }; | 215 }; |
216 | 216 |
217 } // namespace crashpad | 217 } // namespace crashpad |
218 | 218 |
219 #endif // CRASHPAD_SNAPSHOT_SNAPSHOT_CPU_CONTEXT_H_ | 219 #endif // CRASHPAD_SNAPSHOT_SNAPSHOT_CPU_CONTEXT_H_ |
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