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Issue 25491002: x64: Use a short encoding of addq and subq for 32-bit immediates. (Closed) Base URL: https://dart.googlecode.com/svn/branches/bleeding_edge/dart
Patch Set: Created 7 years, 2 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_X64) 6 #if defined(TARGET_ARCH_X64)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/heap.h" 9 #include "vm/heap.h"
10 #include "vm/memory_region.h" 10 #include "vm/memory_region.h"
(...skipping 1653 matching lines...) Expand 10 before | Expand all | Expand 10 after
1664 EmitRegisterREX(reg, REX_W); 1664 EmitRegisterREX(reg, REX_W);
1665 EmitComplex(0, Operand(reg), imm); 1665 EmitComplex(0, Operand(reg), imm);
1666 } else { 1666 } else {
1667 movq(TMP, imm); 1667 movq(TMP, imm);
1668 addq(reg, TMP); 1668 addq(reg, TMP);
1669 } 1669 }
1670 } 1670 }
1671 1671
1672 1672
1673 void Assembler::addq(const Address& address, const Immediate& imm) { 1673 void Assembler::addq(const Address& address, const Immediate& imm) {
1674 // TODO(srdjan): Implement shorter version for imm32. 1674 if (imm.is_int32()) {
1675 movq(TMP, imm); 1675 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1676 addq(address, TMP); 1676 EmitOperandREX(0, address, REX_W);
1677 EmitComplex(0, Operand(address), imm);
1678 } else {
1679 movq(TMP, imm);
1680 addq(address, TMP);
1681 }
1677 } 1682 }
1678 1683
1679 1684
1680 void Assembler::addq(const Address& address, Register reg) { 1685 void Assembler::addq(const Address& address, Register reg) {
1681 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1686 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1682 EmitOperandREX(reg, address, REX_W); 1687 EmitOperandREX(reg, address, REX_W);
1683 EmitUint8(0x01); 1688 EmitUint8(0x01);
1684 EmitOperand(reg & 7, address); 1689 EmitOperand(reg & 7, address);
1685 } 1690 }
1686 1691
(...skipping 141 matching lines...) Expand 10 before | Expand all | Expand 10 after
1828 1833
1829 void Assembler::subq(const Address& address, Register reg) { 1834 void Assembler::subq(const Address& address, Register reg) {
1830 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1835 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1831 EmitOperandREX(reg, address, REX_W); 1836 EmitOperandREX(reg, address, REX_W);
1832 EmitUint8(0x29); 1837 EmitUint8(0x29);
1833 EmitOperand(reg & 7, address); 1838 EmitOperand(reg & 7, address);
1834 } 1839 }
1835 1840
1836 1841
1837 void Assembler::subq(const Address& address, const Immediate& imm) { 1842 void Assembler::subq(const Address& address, const Immediate& imm) {
1838 // TODO(srdjan): Implement shorter version for imm32. 1843 if (imm.is_int32()) {
1839 movq(TMP, imm); 1844 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1840 subq(address, TMP); 1845 EmitOperandREX(0, address, REX_W);
1846 EmitComplex(5, Operand(address), imm);
1847 } else {
1848 movq(TMP, imm);
1849 subq(address, TMP);
1850 }
1841 } 1851 }
1842 1852
1843 1853
1844 void Assembler::shll(Register reg, const Immediate& imm) { 1854 void Assembler::shll(Register reg, const Immediate& imm) {
1845 EmitGenericShift(false, 4, reg, imm); 1855 EmitGenericShift(false, 4, reg, imm);
1846 } 1856 }
1847 1857
1848 1858
1849 void Assembler::shll(Register operand, Register shifter) { 1859 void Assembler::shll(Register operand, Register shifter) {
1850 EmitGenericShift(false, 4, operand, shifter); 1860 EmitGenericShift(false, 4, operand, shifter);
(...skipping 1224 matching lines...) Expand 10 before | Expand all | Expand 10 after
3075 3085
3076 3086
3077 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3087 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3078 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); 3088 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
3079 return xmm_reg_names[reg]; 3089 return xmm_reg_names[reg];
3080 } 3090 }
3081 3091
3082 } // namespace dart 3092 } // namespace dart
3083 3093
3084 #endif // defined TARGET_ARCH_X64 3094 #endif // defined TARGET_ARCH_X64
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