[Turbofan] Add ARM NEON instructions for implementing SIMD.

src/arm/constants-arm.h

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM_CONSTANTS_ARM_H_
 #define V8_ARM_CONSTANTS_ARM_H_
 
 #include <stdint.h>
 
 #include "src/base/logging.h"
@@ skipping 172 matching lines @@
   U = 1 << 23,  // Positive (or negative) offset/index.
   P = 1 << 24,  // Offset/pre-indexed addressing (or post-indexed addressing).
   I = 1 << 25,  // Immediate shifter operand (or not).
   B0 = 1 << 0,
   B4 = 1 << 4,
   B5 = 1 << 5,
   B6 = 1 << 6,
   B7 = 1 << 7,
   B8 = 1 << 8,
   B9 = 1 << 9,
+  B10 = 1 << 10,
   B12 = 1 << 12,
   B16 = 1 << 16,
   B17 = 1 << 17,
   B18 = 1 << 18,
   B19 = 1 << 19,
   B20 = 1 << 20,
   B21 = 1 << 21,
   B22 = 1 << 22,
   B23 = 1 << 23,
   B24 = 1 << 24,
   B25 = 1 << 25,
   B26 = 1 << 26,
   B27 = 1 << 27,
   B28 = 1 << 28,
 
   // Instruction bit masks.
   kCondMask = 15 << 28,
   kALUMask = 0x6f << 21,
   kRdMask = 15 << 12,  // In str instruction.
   kCoprocessorMask = 15 << 8,
   kOpCodeMask = 15 << 21,  // In data-processing instructions.
   kImm24Mask = (1 << 24) - 1,
   kImm16Mask = (1 << 16) - 1,
   kImm8Mask = (1 << 8) - 1,
   kOff12Mask = (1 << 12) - 1,
   kOff8Mask = (1 << 8) - 1
 };
 
-
 enum BarrierOption {
   OSHLD = 0x1,
   OSHST = 0x2,
   OSH = 0x3,
   NSHLD = 0x5,
   NSHST = 0x6,
   NSH = 0x7,
   ISHLD = 0x9,
   ISHST = 0xa,
   ISH = 0xb,
@@ skipping 88 matching lines @@
 
 // Coprocessor load/store operand size.
 enum LFlag {
   Long  = 1 << 22,  // Long load/store coprocessor.
   Short = 0 << 22   // Short load/store coprocessor.
 };
 
 
 // NEON data type
 enum NeonDataType {
-  NeonS8 = 0x1,   // U = 0, imm3 = 0b001
-  NeonS16 = 0x2,  // U = 0, imm3 = 0b010
-  NeonS32 = 0x4,  // U = 0, imm3 = 0b100
+  NeonOtherDataType = 0,
+  NeonS8 = 0x1,             // U = 0, imm3 = 0b001
+  NeonS16 = 0x2,            // U = 0, imm3 = 0b010
+  NeonS32 = 0x4,            // U = 0, imm3 = 0b100
   NeonU8 = 1 << 24 | 0x1,   // U = 1, imm3 = 0b001
   NeonU16 = 1 << 24 | 0x2,  // U = 1, imm3 = 0b010
-  NeonU32 = 1 << 24 | 0x4,   // U = 1, imm3 = 0b100
+  NeonU32 = 1 << 24 | 0x4,  // U = 1, imm3 = 0b100
   NeonDataTypeSizeMask = 0x7,
   NeonDataTypeUMask = 1 << 24
 };
 
 enum NeonListType {
   nlt_1 = 0x7,
   nlt_2 = 0xA,
   nlt_3 = 0x6,
   nlt_4 = 0x2
 };
@@ skipping 314 matching lines @@
   // Instructions are read of out a code stream. The only way to get a
   // reference to an instruction is to convert a pointer. There is no way
   // to allocate or create instances of class Instruction.
   // Use the At(pc) function to create references to Instruction.
   static Instruction* At(byte* pc) {
     return reinterpret_cast<Instruction*>(pc);
   }
 
 
  private:
-  // Join split register codes, depending on single or double precision.
+  // Join split register codes, depending on register precision.
   // four_bit is the position of the least-significant bit of the four
   // bit specifier. one_bit is the position of the additional single bit
   // specifier.
   inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) {
     if (pre == kSinglePrecision) {
       return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
     } else {
       int reg_num = (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
       if (pre == kDoublePrecision) {
         return reg_num;
@@ skipping 41 matching lines @@
 
  private:
   static const char* names_[kNumVFPRegisters];
 };
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_CONSTANTS_ARM_H_