[Turbofan] Add ARM NEON instructions for implementing SIMD.

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 922 matching lines @@
       COMPARE(vst1(Neon16, NeonListOperand(d17, 4), NeonMemOperand(r9)),
               "f449124f       vst1.16 {d17, d18, d19, d20}, [r9]");
       COMPARE(vmovl(NeonU8, q3, d1),
               "f3886a11       vmovl.u8 q3, d1");
       COMPARE(vmovl(NeonU8, q4, d2),
               "f3888a12       vmovl.u8 q4, d2");
       COMPARE(vmov(q0, q15),
               "f22e01fe       vmov q0, q15");
       COMPARE(vmov(q8, q9),
               "f26201f2       vmov q8, q9");
+      COMPARE(vmvn(q0, q15),
+              "f3b005ee       vmvn q0, q15");
+      COMPARE(vmvn(q8, q9),
+              "f3f005e2       vmvn q8, q9");
       COMPARE(vswp(d0, d31),
               "f3b2002f       vswp d0, d31");
       COMPARE(vswp(d16, d14),
               "f3f2000e       vswp d16, d14");
       COMPARE(vswp(q0, q15),
               "f3b2006e       vswp q0, q15");
       COMPARE(vswp(q8, q9),
               "f3f20062       vswp q8, q9");
+      COMPARE(vdup(q0, r0, Neon8),
+              "eee00b10       vdup.8 q0, r0");
+      COMPARE(vdup(q1, r4, Neon16),
+              "eea24b30       vdup.16 q1, r4");
+      COMPARE(vdup(q15, r1, Neon32),
+              "eeae1b90       vdup.32 q15, r1");
+      COMPARE(vdup(q0, s3),
+              "f3bc0c41       vdup q0, d1[1]");
+      COMPARE(vdup(q15, s2),
+              "f3f4ec41       vdup q15, d1[0]");
+      COMPARE(vcvt_f32_s32(q15, q1),
+              "f3fbe642       vcvt.f32.s32 q15, q1");
+      COMPARE(vcvt_f32_u32(q8, q9),
+              "f3fb06e2       vcvt.f32.u32 q8, q9");
+      COMPARE(vcvt_s32_f32(q15, q1),
+              "f3fbe742       vcvt.s32.f32 q15, q1");
+      COMPARE(vcvt_u32_f32(q8, q9),
+              "f3fb07e2       vcvt.u32.f32 q8, q9");
       COMPARE(veor(d0, d1, d2),
               "f3010112       veor d0, d1, d2");
       COMPARE(veor(d0, d30, d31),
               "f30e01bf       veor d0, d30, d31");
       COMPARE(veor(q0, q1, q2),
               "f3020154       veor q0, q1, q2");
       COMPARE(veor(q15, q0, q8),
               "f340e170       veor q15, q0, q8");
+      COMPARE(vadd(q15, q0, q8),
+              "f240ed60       vadd.f32 q15, q0, q8");
+      COMPARE(vadd(q0, q1, q2, Neon8),
+              "f2020844       vadd.i8 q0, q1, q2");
+      COMPARE(vadd(q1, q2, q8, Neon16),
+              "f2142860       vadd.i16 q1, q2, q8");
+      COMPARE(vadd(q15, q0, q8, Neon32),
+              "f260e860       vadd.i32 q15, q0, q8");
+      COMPARE(vsub(q15, q0, q8),
+              "f260ed60       vsub.f32 q15, q0, q8");
+      COMPARE(vsub(q0, q1, q2, Neon8),
+              "f3020844       vsub.i8 q0, q1, q2");
+      COMPARE(vsub(q1, q2, q8, Neon16),
+              "f3142860       vsub.i16 q1, q2, q8");
+      COMPARE(vsub(q15, q0, q8, Neon32),
+              "f360e860       vsub.i32 q15, q0, q8");
+      COMPARE(vtst(q0, q1, q2, Neon8),
+              "f2020854       vtst.i8 q0, q1, q2");
+      COMPARE(vtst(q1, q2, q8, Neon16),
+              "f2142870       vtst.i16 q1, q2, q8");
+      COMPARE(vtst(q15, q0, q8, Neon32),
+              "f260e870       vtst.i32 q15, q0, q8");
+      COMPARE(vceq(q0, q1, q2, Neon8),
+              "f3020854       vceq.i8 q0, q1, q2");
+      COMPARE(vceq(q1, q2, q8, Neon16),
+              "f3142870       vceq.i16 q1, q2, q8");
+      COMPARE(vceq(q15, q0, q8, Neon32),
+              "f360e870       vceq.i32 q15, q0, q8");
+      COMPARE(vbsl(q0, q1, q2),
+              "f3120154       vbsl q0, q1, q2");
+      COMPARE(vbsl(q15, q0, q8),
+              "f350e170       vbsl q15, q0, q8");
+      COMPARE(vtbl(d0, NeonListOperand(d1, 1), d2),
+              "f3b10802       vtbl d0, {d1}, d2");

[Rodolph Perfetta (ARM), 2016/12/08 18:08:28]

vtbl.8/vtbx.8

[bbudge, 2016/12/10 21:33:04]

Done.

+      COMPARE(vtbl(d31, NeonListOperand(d0, 2), d4),
+              "f3f0f904       vtbl d31, {d0, d1}, d4");
+      COMPARE(vtbl(d15, NeonListOperand(d1, 3), d5),
+              "f3b1fa05       vtbl d15, {d1, d2, d3}, d5");
+      COMPARE(vtbx(d0, NeonListOperand(d1, 1), d2),
+              "f3b10842       vtbx d0, {d1}, d2");
+      COMPARE(vtbx(d31, NeonListOperand(d0, 2), d4),
+              "f3f0f944       vtbx d31, {d0, d1}, d4");
+      COMPARE(vtbx(d15, NeonListOperand(d1, 3), d5),
+              "f3b1fa45       vtbx d15, {d1, d2, d3}, d5");

[Rodolph Perfetta (ARM), 2016/12/08 18:08:28]

it woudl be nice to have a test with a list of 4 registers.

[bbudge, 2016/12/10 21:33:04]

Done.

   }
 
   VERIFY_RUN();
 }
 
 
 TEST(LoadStore) {
   SET_UP();
 
   COMPARE(ldrb(r0, MemOperand(r1)),
@@ skipping 270 matching lines @@
 
   COMPARE(ldrexb(r0, r1), "e1d10f9f       ldrexb r0, [r1]");
   COMPARE(strexb(r0, r1, r2), "e1c20f91       strexb r0, r1, [r2]");
   COMPARE(ldrexh(r0, r1), "e1f10f9f       ldrexh r0, [r1]");
   COMPARE(strexh(r0, r1, r2), "e1e20f91       strexh r0, r1, [r2]");
   COMPARE(ldrex(r0, r1), "e1910f9f       ldrex r0, [r1]");
   COMPARE(strex(r0, r1, r2), "e1820f91       strex r0, r1, [r2]");
 
   VERIFY_RUN();
 }