[Turbofan] Add ARM NEON instructions for implementing SIMD.

src/arm/assembler-arm.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 622 matching lines @@
 
   Register rn_;  // base
   Register rm_;  // register increment
   int align_;
 };
 
 
 // Class NeonListOperand represents a list of NEON registers
 class NeonListOperand BASE_EMBEDDED {
  public:
-  explicit NeonListOperand(DoubleRegister base, int registers_count = 1);
+  explicit NeonListOperand(DoubleRegister base, int register_count = 1)
+    : base_(base), register_count_(register_count) {}
+  explicit NeonListOperand(QwNeonRegister q_reg)
+    : base_(q_reg.low()), register_count_(2) {}
   DoubleRegister base() const { return base_; }
-  NeonListType type() const { return type_; }
+  int register_count() { return register_count_; }
+  int len() const { return register_count_ - 1; }

[Rodolph Perfetta (ARM), 2016/12/08 18:08:28]

len -> length

[bbudge, 2016/12/10 21:33:04]

Done.

+  NeonListType type() const {
+    switch (register_count_) {
+      default: UNREACHABLE();
+      // Fall through.
+      case 1: return nlt_1;
+      case 2: return nlt_2;
+      case 3: return nlt_3;
+      case 4: return nlt_4;
+    }
+  }
  private:
   DoubleRegister base_;
-  NeonListType type_;
+  int register_count_;
 };
 
 
 struct VmovIndex {
   unsigned char index;
 };
 const VmovIndex VmovIndexLo = { 0 };
 const VmovIndex VmovIndexHi = { 1 };
 
 class Assembler : public AssemblerBase {
@@ skipping 664 matching lines @@
   // All these APIs support D0 to D31 and Q0 to Q15.
   void vld1(NeonSize size,
             const NeonListOperand& dst,
             const NeonMemOperand& src);
   void vst1(NeonSize size,
             const NeonListOperand& src,
             const NeonMemOperand& dst);
   void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src);
 
   void vmov(const QwNeonRegister dst, const QwNeonRegister src);
+  void vmvn(const QwNeonRegister dst, const QwNeonRegister src);
   void vswp(DwVfpRegister dst, DwVfpRegister src);
   void vswp(QwNeonRegister dst, QwNeonRegister src);
+  // vdup conditional execution isn't supported.
+  void vdup(const QwNeonRegister dst, const Register src, NeonSize size);

[Rodolph Perfetta (ARM), 2016/12/08 18:08:28]

in other instructions like vmovl the size qualifier is the first argument to be
closer to the assembly syntax

[bbudge, 2016/12/10 21:33:04]

Done.

+  void vdup(const QwNeonRegister dst, const SwVfpRegister src);

[Rodolph Perfetta (ARM), 2016/12/08 18:08:28]

this is a special case of vdup.size dst, src[index]. Any reason why we wouldn't
want to support for full instruction? That would give us access to higher D
registers for example. I am just asking, if this is the only useful case for now
that is fine by me.

[bbudge, 2016/12/10 21:33:04]

This is enough for Wasm, so I'll leave it as is.

+
+  void vcvt_f32_s32(const QwNeonRegister dst, const QwNeonRegister src);
+  void vcvt_f32_u32(const QwNeonRegister dst, const QwNeonRegister src);
+  void vcvt_s32_f32(const QwNeonRegister dst, const QwNeonRegister src);
+  void vcvt_u32_f32(const QwNeonRegister dst, const QwNeonRegister src);
+
   void veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2);
   void veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
+  void vadd(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2);
+  void vadd(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2, NeonSize size);

[Rodolph Perfetta (ARM), 2016/12/08 18:08:28]

how about having the size as the first

[bbudge, 2016/12/10 21:33:04]

Done.

+  void vsub(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2);
+  void vsub(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2, NeonSize size);

[Rodolph Perfetta (ARM), 2016/12/08 18:08:27]

ditto

[bbudge, 2016/12/10 21:33:04]

Done.

+  void vtst(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2, NeonSize size);

[Rodolph Perfetta (ARM), 2016/12/08 18:08:28]

ditto

[bbudge, 2016/12/10 21:33:04]

Done.

+  void vceq(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2, NeonSize size);

[Rodolph Perfetta (ARM), 2016/12/08 18:08:28]

ditto

[bbudge, 2016/12/10 21:33:04]

Done.

+  void vbsl(const QwNeonRegister dst, const QwNeonRegister src1,
+            const QwNeonRegister src2);
+  void vtbl(const DwVfpRegister dst, const NeonListOperand& list,
+            const DwVfpRegister index);
+  void vtbx(const DwVfpRegister dst, const NeonListOperand& list,
+            const DwVfpRegister index);
 
   // Pseudo instructions
 
   // Different nop operations are used by the code generator to detect certain
   // states of the generated code.
   enum NopMarkerTypes {
     NON_MARKING_NOP = 0,
     DEBUG_BREAK_NOP,
     // IC markers.
     PROPERTY_ACCESS_INLINED,
@@ skipping 385 matching lines @@
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_ASSEMBLER_ARM_H_