MIPS: Use JIC/JIALC offset when possible

src/mips/assembler-mips.cc

Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index ed3f50a817d7d3315bbc44d200fc3f661fcce69a..8558767d2da774b8d80e4e7eea264f4f79dc6862 100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -2077,6 +2077,7 @@ void Assembler::lui(Register rd, int32_t j) {
 void Assembler::aui(Register rt, Register rs, int32_t j) {
   // This instruction uses same opcode as 'lui'. The difference in encoding is
   // 'lui' has zero reg. for rs field.
+  DCHECK(IsMipsArchVariant(kMips32r6));
   DCHECK(!(rs.is(zero_reg)));
   DCHECK(is_uint16(j));
   GenInstrImmediate(LUI, rs, rt, j);
@@ -3746,11 +3747,17 @@ void Assembler::CheckTrampolinePool() {
 Address Assembler::target_address_at(Address pc) {
   Instr instr1 = instr_at(pc);
   Instr instr2 = instr_at(pc + kInstrSize);
-  // Interpret 2 instructions generated by li: lui/ori
-  if (IsLui(instr1) && IsOri(instr2)) {
-    // Assemble the 32 bit value.
-    return reinterpret_cast<Address>((GetImmediate16(instr1) << kLuiShift) |
-                                     GetImmediate16(instr2));
+  // Interpret 2 instructions generated by li (lui/ori) or optimized pairs
+  // lui/jic, aui/jic or lui/jialc.
+  if (IsLui(instr1)) {
+    if (IsOri(instr2)) {
+      // Assemble the 32 bit value.
+      return reinterpret_cast<Address>((GetImmediate16(instr1) << kLuiShift) |
+                                       GetImmediate16(instr2));
+    } else if (IsJicOrJialc(instr2)) {
+      // Assemble the 32 bit value.
+      return reinterpret_cast<Address>(CreateTargetAddress(instr1, instr2));
+    }
   }
 
   // We should never get here, force a bad address if we do.