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Side by Side Diff: src/mips/assembler-mips.h

Issue 25420002: MIPS: Let the register allocator handle the context register. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Added missing ASSERT. Created 7 years, 2 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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65 // mode. This way we get the compile-time error checking in debug mode 65 // mode. This way we get the compile-time error checking in debug mode
66 // and best performance in optimized code. 66 // and best performance in optimized code.
67 67
68 68
69 // ----------------------------------------------------------------------------- 69 // -----------------------------------------------------------------------------
70 // Implementation of Register and FPURegister. 70 // Implementation of Register and FPURegister.
71 71
72 // Core register. 72 // Core register.
73 struct Register { 73 struct Register {
74 static const int kNumRegisters = v8::internal::kNumRegisters; 74 static const int kNumRegisters = v8::internal::kNumRegisters;
75 static const int kMaxNumAllocatableRegisters = 14; // v0 through t7. 75 static const int kMaxNumAllocatableRegisters = 14; // v0 through t6 and cp.
76 static const int kSizeInBytes = 4; 76 static const int kSizeInBytes = 4;
77 static const int kCpRegister = 23; // cp (s7) is the 23rd register.
77 78
78 inline static int NumAllocatableRegisters(); 79 inline static int NumAllocatableRegisters();
79 80
80 static int ToAllocationIndex(Register reg) { 81 static int ToAllocationIndex(Register reg) {
81 return reg.code() - 2; // zero_reg and 'at' are skipped. 82 ASSERT((reg.code() - 2) < (kMaxNumAllocatableRegisters - 1) ||
83 reg.is(from_code(kCpRegister)));
84 return reg.is(from_code(kCpRegister)) ?
85 kMaxNumAllocatableRegisters - 1 : // Return last index for 'cp'.
86 reg.code() - 2; // zero_reg and 'at' are skipped.
82 } 87 }
83 88
84 static Register FromAllocationIndex(int index) { 89 static Register FromAllocationIndex(int index) {
85 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 90 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
86 return from_code(index + 2); // zero_reg and 'at' are skipped. 91 return index == kMaxNumAllocatableRegisters - 1 ?
92 from_code(kCpRegister) : // Last index is always the 'cp' register.
93 from_code(index + 2); // zero_reg and 'at' are skipped.
87 } 94 }
88 95
89 static const char* AllocationIndexToString(int index) { 96 static const char* AllocationIndexToString(int index) {
90 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 97 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
91 const char* const names[] = { 98 const char* const names[] = {
92 "v0", 99 "v0",
93 "v1", 100 "v1",
94 "a0", 101 "a0",
95 "a1", 102 "a1",
96 "a2", 103 "a2",
97 "a3", 104 "a3",
98 "t0", 105 "t0",
99 "t1", 106 "t1",
100 "t2", 107 "t2",
101 "t3", 108 "t3",
102 "t4", 109 "t4",
103 "t5", 110 "t5",
104 "t6", 111 "t6",
105 "t7", 112 "s7",
106 }; 113 };
107 return names[index]; 114 return names[index];
108 } 115 }
109 116
110 static Register from_code(int code) { 117 static Register from_code(int code) {
111 Register r = { code }; 118 Register r = { code };
112 return r; 119 return r;
113 } 120 }
114 121
115 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; } 122 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
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1211 class EnsureSpace BASE_EMBEDDED { 1218 class EnsureSpace BASE_EMBEDDED {
1212 public: 1219 public:
1213 explicit EnsureSpace(Assembler* assembler) { 1220 explicit EnsureSpace(Assembler* assembler) {
1214 assembler->CheckBuffer(); 1221 assembler->CheckBuffer();
1215 } 1222 }
1216 }; 1223 };
1217 1224
1218 } } // namespace v8::internal 1225 } } // namespace v8::internal
1219 1226
1220 #endif // V8_ARM_ASSEMBLER_MIPS_H_ 1227 #endif // V8_ARM_ASSEMBLER_MIPS_H_
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