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Side by Side Diff: runtime/vm/constants_arm64.h

Issue 253623003: Enables all startup code for arm64. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 8 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_CONSTANTS_ARM64_H_ 5 #ifndef VM_CONSTANTS_ARM64_H_
6 #define VM_CONSTANTS_ARM64_H_ 6 #define VM_CONSTANTS_ARM64_H_
7 7
8 #include "platform/assert.h" 8 #include "platform/assert.h"
9 9
10 namespace dart { 10 namespace dart {
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366 }; 366 };
367 367
368 // C3.5.1 368 // C3.5.1
369 enum AddSubShiftExtOp { 369 enum AddSubShiftExtOp {
370 AddSubShiftExtMask = 0x1f000000, 370 AddSubShiftExtMask = 0x1f000000,
371 AddSubShiftExtFixed = DPRegisterFixed | B24, 371 AddSubShiftExtFixed = DPRegisterFixed | B24,
372 ADD = AddSubShiftExtFixed, 372 ADD = AddSubShiftExtFixed,
373 SUB = AddSubShiftExtFixed | B30, 373 SUB = AddSubShiftExtFixed | B30,
374 }; 374 };
375 375
376 // C3.5.6
377 enum ConditionalSelectOp {
378 ConditionalSelectMask = 0x1fe00000,
379 ConditionalSelectFixed = DPRegisterFixed | B28 | B23,
380 CSEL = ConditionalSelectFixed,
381 };
382
376 // C3.5.8 383 // C3.5.8
377 enum MiscDP2SourceOp { 384 enum MiscDP2SourceOp {
378 MiscDP2SourceMask = 0x5fe00000, 385 MiscDP2SourceMask = 0x5fe00000,
379 MiscDP2SourceFixed = DPRegisterFixed | B28 | B23 | B22, 386 MiscDP2SourceFixed = DPRegisterFixed | B28 | B23 | B22,
380 UDIV = MiscDP2SourceFixed | B11, 387 UDIV = MiscDP2SourceFixed | B11,
381 SDIV = MiscDP2SourceFixed | B11 | B10, 388 SDIV = MiscDP2SourceFixed | B11 | B10,
382 LSLV = MiscDP2SourceFixed | B13, 389 LSLV = MiscDP2SourceFixed | B13,
383 LSRV = MiscDP2SourceFixed | B13 | B10, 390 LSRV = MiscDP2SourceFixed | B13 | B10,
384 ASRV = MiscDP2SourceFixed | B13 | B11, 391 ASRV = MiscDP2SourceFixed | B13 | B11,
385 }; 392 };
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419 _V(TestAndBranch) \ 426 _V(TestAndBranch) \
420 _V(UnconditionalBranch) \ 427 _V(UnconditionalBranch) \
421 _V(UnconditionalBranchReg) \ 428 _V(UnconditionalBranchReg) \
422 _V(LoadStoreReg) \ 429 _V(LoadStoreReg) \
423 _V(LoadRegLiteral) \ 430 _V(LoadRegLiteral) \
424 _V(AddSubImm) \ 431 _V(AddSubImm) \
425 _V(LogicalImm) \ 432 _V(LogicalImm) \
426 _V(MoveWide) \ 433 _V(MoveWide) \
427 _V(PCRel) \ 434 _V(PCRel) \
428 _V(AddSubShiftExt) \ 435 _V(AddSubShiftExt) \
436 _V(ConditionalSelect) \
429 _V(MiscDP2Source) \ 437 _V(MiscDP2Source) \
430 _V(MiscDP3Source) \ 438 _V(MiscDP3Source) \
431 _V(LogicalShift) \ 439 _V(LogicalShift) \
432 440
433 441
434 enum Shift { 442 enum Shift {
435 kNoShift = -1, 443 kNoShift = -1,
436 LSL = 0, // Logical shift left 444 LSL = 0, // Logical shift left
437 LSR = 1, // Logical shift right 445 LSR = 1, // Logical shift right
438 ASR = 2, // Arithmetic shift right 446 ASR = 2, // Arithmetic shift right
(...skipping 64 matching lines...) Expand 10 before | Expand all | Expand 10 after
503 kImm16Mask = 0xffff << kImm16Shift, 511 kImm16Mask = 0xffff << kImm16Shift,
504 kImm19Shift = 5, 512 kImm19Shift = 5,
505 kImm19Bits = 19, 513 kImm19Bits = 19,
506 kImm19Mask = 0x7ffff << kImm19Shift, 514 kImm19Mask = 0x7ffff << kImm19Shift,
507 kImm26Shift = 0, 515 kImm26Shift = 0,
508 kImm26Bits = 26, 516 kImm26Bits = 26,
509 517
510 kCondShift = 0, 518 kCondShift = 0,
511 kCondBits = 4, 519 kCondBits = 4,
512 520
521 kSelCondShift = 12,
522 kSelCondBits = 4,
523
513 // Bitfield immediates. 524 // Bitfield immediates.
514 kNShift = 22, 525 kNShift = 22,
515 kNBits = 1, 526 kNBits = 1,
516 kImmRShift = 16, 527 kImmRShift = 16,
517 kImmRBits = 6, 528 kImmRBits = 6,
518 kImmSShift = 10, 529 kImmSShift = 10,
519 kImmSBits = 6, 530 kImmSBits = 6,
520 531
521 kHWShift = 21, 532 kHWShift = 21,
522 kHWBits = 2, 533 kHWBits = 2,
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668 inline int Imm19Field() const { return Bits(kImm19Shift, kImm19Bits); } 679 inline int Imm19Field() const { return Bits(kImm19Shift, kImm19Bits); }
669 inline int64_t SImm19Field() const { 680 inline int64_t SImm19Field() const {
670 return (static_cast<int32_t>(Imm19Field()) << 13) >> 13; } 681 return (static_cast<int32_t>(Imm19Field()) << 13) >> 13; }
671 inline int Imm26Field() const { return Bits(kImm26Shift, kImm26Bits); } 682 inline int Imm26Field() const { return Bits(kImm26Shift, kImm26Bits); }
672 inline int64_t SImm26Field() const { 683 inline int64_t SImm26Field() const {
673 return (static_cast<int32_t>(Imm26Field()) << 6) >> 6; } 684 return (static_cast<int32_t>(Imm26Field()) << 6) >> 6; }
674 685
675 inline Condition ConditionField() const { 686 inline Condition ConditionField() const {
676 return static_cast<Condition>(Bits(kCondShift, kCondBits)); 687 return static_cast<Condition>(Bits(kCondShift, kCondBits));
677 } 688 }
689 inline Condition SelectConditionField() const {
690 return static_cast<Condition>(Bits(kSelCondShift, kSelCondBits));
691 }
678 692
679 // Shift and Extend. 693 // Shift and Extend.
680 inline bool IsShift() const { 694 inline bool IsShift() const {
681 return IsLogicalShiftOp() || (Bit(kAddShiftExtendShift) == 0); 695 return IsLogicalShiftOp() || (Bit(kAddShiftExtendShift) == 0);
682 } 696 }
683 inline bool IsExtend() const { 697 inline bool IsExtend() const {
684 return !IsLogicalShiftOp() && (Bit(kAddShiftExtendShift) == 1); 698 return !IsLogicalShiftOp() && (Bit(kAddShiftExtendShift) == 1);
685 } 699 }
686 inline Shift ShiftTypeField() const { 700 inline Shift ShiftTypeField() const {
687 return static_cast<Shift>(Bits(kShiftTypeShift, kShiftTypeBits)); } 701 return static_cast<Shift>(Bits(kShiftTypeShift, kShiftTypeBits)); }
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794 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } 808 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
795 809
796 private: 810 private:
797 DISALLOW_ALLOCATION(); 811 DISALLOW_ALLOCATION();
798 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); 812 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
799 }; 813 };
800 814
801 } // namespace dart 815 } // namespace dart
802 816
803 #endif // VM_CONSTANTS_ARM64_H_ 817 #endif // VM_CONSTANTS_ARM64_H_
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