Enables all startup code for arm64.

runtime/vm/simulator_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <math.h>  // for isnan.
 #include <setjmp.h>
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
@@ skipping 113 matching lines @@
       "r28", "r29", "r30",
 
       "ip0", "ip1", "pp",  "ctx", "fp",  "lr",  "sp", "zr",
   };
   static const Register kRegisters[] = {
       R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,
       R8,  R9,  R10, R11, R12, R13, R14, R15,
       R16, R17, R18, R19, R20, R21, R22, R23,
       R24, R25, R26, R27, R28, R29, R30,
 
-      IP0, IP1, PP, CTX, FP, LR, SP, ZR,
+      IP0, IP1, PP, CTX, FP, LR, R31, ZR,
   };
   ASSERT(ARRAY_SIZE(kNames) == ARRAY_SIZE(kRegisters));
   for (unsigned i = 0; i < ARRAY_SIZE(kNames); i++) {
     if (strcmp(kNames[i], name) == 0) {
       return kRegisters[i];
     }
   }
   return kNoRegister;
 }
 
 
 bool SimulatorDebugger::GetValue(char* desc, int64_t* value) {
   Register reg = LookupCpuRegisterByName(desc);
   if (reg != kNoRegister) {
+    if (reg == ZR) {
+      *value = 0;
+      return true;
+    }
     *value = sim_->get_register(reg);
     return true;
   }
   if (desc[0] == '*') {
     int64_t addr;
     if (GetValue(desc + 1, &addr)) {
       if (Simulator::IsIllegalAddress(addr)) {
         return false;
       }
       *value = *(reinterpret_cast<int64_t*>(addr));
@@ skipping 426 matching lines @@
   dbg.Stop(instr, buffer);
   // The debugger will return control in non-interactive mode.
   FATAL("Cannot continue execution after illegal memory access.");
 }
 
 
 // The ARMv8 manual advises that an unaligned access may generate a fault,
 // and if not, will likely take a number of additional cycles to execute,
 // so let's just not generate any.
 void Simulator::UnalignedAccess(const char* msg, uword addr, Instr* instr) {
-  char buffer[64];
+  char buffer[128];
   snprintf(buffer, sizeof(buffer),
            "unaligned %s at 0x%" Px ", pc=%p\n", msg, addr, instr);
   SimulatorDebugger dbg(this);
   dbg.Stop(instr, buffer);
   // The debugger will not be able to single step past this instruction, but
   // it will be possible to disassemble the code and inspect registers.
   FATAL("Cannot continue execution after unaligned access.");
 }
 
 
 void Simulator::UnimplementedInstruction(Instr* instr) {
-  char buffer[64];
-  snprintf(buffer, sizeof(buffer), "Unimplemented instruction: pc=%p\n", instr);
+  char buffer[128];
+  snprintf(buffer, sizeof(buffer),
+      "Unimplemented instruction: at %p, last_pc=0x%"Px"\n",
+      instr, get_last_pc());
   SimulatorDebugger dbg(this);
   dbg.Stop(instr, buffer);
   FATAL("Cannot continue execution after unimplemented instruction.");
 }
 
 
 // Returns the top of the stack area to enable checking for stack pointer
 // validity.
 uword Simulator::StackTop() const {
   // To be safe in potential stack underflows we leave some buffer above and
@@ skipping 384 matching lines @@
   } else {
     // Format(instr, "cbnz'sf 'rt, 'dest19");
     if (rt_val != 0) {
       set_pc(dest);
     }
   }
 }
 
 
 bool Simulator::ConditionallyExecute(Instr* instr) {
-  switch (instr->ConditionField()) {
+  Condition cond;
+  if (instr->IsConditionalSelectOp()) {
+    cond = instr->SelectConditionField();
+  } else {
+    cond = instr->ConditionField();
+  }
+  switch (cond) {
     case EQ: return z_flag_;
     case NE: return !z_flag_;
     case CS: return c_flag_;
     case CC: return !c_flag_;
     case MI: return n_flag_;
     case PL: return !n_flag_;
     case VS: return v_flag_;
     case VC: return !v_flag_;
     case HI: return c_flag_ && !z_flag_;
     case LS: return !c_flag_ || z_flag_;
@@ skipping 787 matching lines @@
       const int32_t ra_val = get_wregister(ra, R31IsZR);
       const int32_t alu_out = ra_val + (rn_val * rm_val);
       set_wregister(rd, alu_out, R31IsZR);
     }
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
 
+void Simulator::DecodeConditionalSelect(Instr* instr) {
+  if ((instr->Bits(29, 2) == 0) && (instr->Bits(10, 2) == 0)) {
+    // Format(instr, "mov'sf'cond 'rd, 'rn, 'rm");
+    const Register rd = instr->RdField();
+    const Register rn = instr->RnField();
+    const Register rm = instr->RmField();
+    if (instr->SFField() == 1) {
+      int64_t res = 0;
+      if (ConditionallyExecute(instr)) {
+        res = get_register(rn, instr->RnMode());
+      } else {
+        res = get_register(rm, R31IsZR);
+      }
+      set_register(rd, res, instr->RdMode());
+    } else {
+      int32_t res = 0;
+      if (ConditionallyExecute(instr)) {
+        res = get_wregister(rn, instr->RnMode());
+      } else {
+        res = get_wregister(rm, R31IsZR);
+      }
+      set_wregister(rd, res, instr->RdMode());
+    }
+
+  } else {
+    UnimplementedInstruction(instr);
+  }
+}
+
+
 void Simulator::DecodeDPRegister(Instr* instr) {
   if (instr->IsAddSubShiftExtOp()) {
     DecodeAddSubShiftExt(instr);
   } else if (instr->IsLogicalShiftOp()) {
     DecodeLogicalShift(instr);
   } else if (instr->IsMiscDP2SourceOp()) {
     DecodeMiscDP2Source(instr);
   } else if (instr->IsMiscDP3SourceOp()) {
     DecodeMiscDP3Source(instr);
+  } else if (instr->IsConditionalSelectOp()) {
+    DecodeConditionalSelect(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
 
 void Simulator::DecodeDPSimd1(Instr* instr) {
   UnimplementedInstruction(instr);
 }
 
@@ skipping 15 matching lines @@
   if (instr->IsDPImmediateOp()) {
     DecodeDPImmediate(instr);
   } else if (instr->IsCompareBranchOp()) {
     DecodeCompareBranch(instr);
   } else if (instr->IsLoadStoreOp()) {
     DecodeLoadStore(instr);
   } else if (instr->IsDPRegisterOp()) {
     DecodeDPRegister(instr);
   } else if (instr->IsDPSimd1Op()) {
     DecodeDPSimd1(instr);
+  } else if (instr->IsDPSimd2Op()) {
+    DecodeDPSimd2(instr);
   } else {
-    ASSERT(instr->IsDPSimd2Op());
-    DecodeDPSimd2(instr);
+    UnimplementedInstruction(instr);
   }
 
   if (!pc_modified_) {
     set_pc(reinterpret_cast<int64_t>(instr) + Instr::kInstrSize);
   }
 }
 
 
 void Simulator::Execute() {
   // Get the PC to simulate. Cannot use the accessor here as we need the
@@ skipping 124 matching lines @@
   int64_t return_value;
   return_value = get_register(R0);
   return return_value;
 }
 
 }  // namespace dart
 
 #endif  // !defined(HOST_ARCH_ARM64)
 
 #endif  // defined TARGET_ARCH_ARM64