Enables all startup code for arm64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 137 matching lines @@
   // PC-relative load address.
   static Address PC(int32_t pc_off) {
     ASSERT(CanHoldOffset(pc_off, PCOffset));
     Address addr;
     addr.encoding_ = (((pc_off >> 2) << kImm19Shift) & kImm19Mask);
     addr.base_ = kNoRegister;
     addr.type_ = PCOffset;
     return addr;
   }
 
+  enum Scaling {
+    Unscaled,
+    Scaled,
+  };
+
   // Base register rn with offset rm. rm is sign-extended according to ext.
   // If ext is UXTX, rm may be optionally scaled by the
   // Log2OperandSize (specified by the instruction).
-  Address(Register rn, Register rm, Extend ext = UXTX, bool scaled = false) {
+  Address(Register rn, Register rm,
+          Extend ext = UXTX, Scaling scale = Unscaled) {
     ASSERT((rn != R31) && (rn != ZR));
     ASSERT((rm != R31) && (rm != SP));
-    ASSERT(!scaled || (ext == UXTX));  // Can only scale when ext = UXTX.
+    // Can only scale when ext = UXTX.
+    ASSERT((scale != Scaled) || (ext == UXTX));
     ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
     const Register crn = ConcreteRegister(rn);
     const Register crm = ConcreteRegister(rm);
-    const int32_t s = scaled ? B12 : 0;
+    const int32_t s = (scale == Scaled) ? B12 : 0;
     encoding_ =
         B21 | B11 | s |
         (static_cast<int32_t>(crn) << kRnShift) |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(ext) << kExtendTypeShift);
     type_ = Reg;
     base_ = crn;
   }
 
  private:
@@ skipping 357 matching lines @@
       ASSERT(((a.type() != Address::PreIndex) &&
               (a.type() != Address::PostIndex)) ||
              (rt != a.base()));
       EmitLoadStoreReg(LDR, rt, a, sz);
     }
   }
   void str(Register rt, Address a, OperandSize sz = kDoubleWord) {
     EmitLoadStoreReg(STR, rt, a, sz);
   }
 
+  // Conditional select.
+  void csel(Register rd, Register rn, Register rm, Condition cond) {
+    EmitCoditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
+  }
+
   // Comparison.
   // rn cmp o.
   // For add and sub, to use SP for rn, o must be of type Operand::Extend.
   // For an unmodified rm in this case, use Operand(rm, UXTX, 0);
   void cmp(Register rn, Operand o) {
     subs(ZR, rn, o);
   }
   // rn cmp -o.
   void cmn(Register rn, Operand o) {
     adds(ZR, rn, o);
@@ skipping 56 matching lines @@
   void Push(Register reg) {
     ASSERT(reg != PP);  // Only push PP with TagAndPushPP().
     str(reg, Address(SP, -1 * kWordSize, Address::PreIndex));
   }
   void Pop(Register reg) {
     ASSERT(reg != PP);  // Only pop PP with PopAndUntagPP().
     ldr(reg, Address(SP, 1 * kWordSize, Address::PostIndex));
   }
   void TagAndPushPP() {
     // Add the heap object tag back to PP before putting it on the stack.
-    add(PP, PP, Operand(kHeapObjectTag));
-    str(PP, Address(SP, -1 * kWordSize, Address::PreIndex));
+    add(TMP, PP, Operand(kHeapObjectTag));
+    str(TMP, Address(SP, -1 * kWordSize, Address::PreIndex));
   }
   void PopAndUntagPP() {
     ldr(PP, Address(SP, 1 * kWordSize, Address::PostIndex));
     sub(PP, PP, Operand(kHeapObjectTag));
   }
   void tst(Register rn, Operand o) {
     ands(ZR, rn, o);
   }
   void tsti(Register rn, uint64_t imm) {
     andis(ZR, rn, imm);
   }
 
   void Lsl(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, LSL, shift));
   }
   void Lsr(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, LSR, shift));
   }
   void Asr(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, ASR, shift));
   }
 
   void SmiUntag(Register reg) {
     Asr(reg, reg, kSmiTagSize);
   }
+  void SmiTag(Register reg) {
+    Lsl(reg, reg, kSmiTagSize);
+  }
 
   // Branching to ExternalLabels.
   void BranchPatchable(const ExternalLabel* label, Register pp) {
     LoadExternalLabel(TMP, label, kPatchable, pp);
     br(TMP);
   }
 
   void Branch(const ExternalLabel* label, Register pp) {
     LoadExternalLabel(TMP, label, kNotPatchable, pp);
     br(TMP);
@@ skipping 47 matching lines @@
   void StoreIntoObjectNoBarrier(Register object,
                                 const Address& dest,
                                 Register value);
   void StoreIntoObjectNoBarrier(Register object,
                                 const Address& dest,
                                 const Object& value);
 
   // Object pool, loading from pool, etc.
   void LoadPoolPointer(Register pp);
 
+  // Index of constant pool entries pointing to debugger stubs.
+  static const int kBreakpointRuntimeCPIndex = 5;
+
   enum Patchability {
     kPatchable,
     kNotPatchable,
   };
 
   void LoadWordFromPoolOffset(Register dst, Register pp, uint32_t offset);
   intptr_t FindExternalLabel(const ExternalLabel* label,
                              Patchability patchable);
   intptr_t FindObject(const Object& obj, Patchability patchable);
   intptr_t FindImmediate(int64_t imm);
   bool CanLoadObjectFromPool(const Object& object);
   bool CanLoadImmediateFromPool(int64_t imm, Register pp);
   void LoadExternalLabel(Register dst, const ExternalLabel* label,
                          Patchability patchable, Register pp);
   void LoadObject(Register dst, const Object& obj, Register pp);
   void LoadDecodableImmediate(Register reg, int64_t imm, Register pp);
   void LoadImmediateFixed(Register reg, int64_t imm);
   void LoadImmediate(Register reg, int64_t imm, Register pp);
 
   void PushObject(const Object& object, Register pp) {
     LoadObject(TMP, object, pp);
     Push(TMP);
   }
 
+  void LoadClassId(Register result, Register object);
+  void LoadClassById(Register result, Register class_id);
+  void LoadClass(Register result, Register object);
+  void CompareClassId(Register object, intptr_t class_id);
+
   void EnterFrame(intptr_t frame_size);
   void LeaveFrame();
 
   void EnterDartFrame(intptr_t frame_size);
   void EnterDartFrameWithInfo(intptr_t frame_size, Register new_pp);
   void EnterOsrFrame(intptr_t extra_size, Register new_pp);
   void LeaveDartFrame();
 
   void EnterCallRuntimeFrame(intptr_t frame_size);
   void LeaveCallRuntimeFrame();
@@ skipping 156 matching lines @@
     Emit(encoding);
   }
 
   int32_t EncodeImm19BranchOffset(int64_t imm, int32_t instr) {
     const int32_t imm32 = static_cast<int32_t>(imm);
     const int32_t off = (((imm32 >> 2) << kImm19Shift) & kImm19Mask);
     return (instr & ~kImm19Mask) | off;
   }
 
   int64_t DecodeImm19BranchOffset(int32_t instr) {
-    const int32_t off = (((instr >> kImm19Shift) & kImm19Shift) << 13) >> 13;
+    const int32_t off = (((instr & kImm19Mask) >> kImm19Shift) << 13) >> 11;
     return static_cast<int64_t>(off);
   }
 
   void EmitCompareAndBranch(CompareAndBranchOp op, Register rt, int64_t imm,
                             OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord));
     ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
     ASSERT((rt != SP) && (rt != R31));
     const Register crt = ConcreteRegister(rt);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
@@ skipping 10 matching lines @@
     ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
     const int32_t encoding =
         op |
         (static_cast<int32_t>(cond) << kCondShift) |
         (((imm >> 2) << kImm19Shift) & kImm19Mask);
     Emit(encoding);
   }
 
   bool CanEncodeImm19BranchOffset(int64_t offset) {
     ASSERT(Utils::IsAligned(offset, 4));
-    return Utils::IsInt(19, offset);
+    return Utils::IsInt(21, offset);
   }
 
   // TODO(zra): Implement far branches. Requires loading large immediates.
   void EmitBranch(ConditionalBranchOp op, Condition cond, Label* label) {
     if (label->IsBound()) {
       const int64_t dest = label->Position() - buffer_.Size();
       ASSERT(CanEncodeImm19BranchOffset(dest));
       EmitConditionalBranch(op, cond, dest);
     } else {
       const int64_t position = buffer_.Size();
@@ skipping 63 matching lines @@
     const int32_t encoding =
         op | loimm | hiimm |
         (static_cast<int32_t>(crd) << kRdShift);
     Emit(encoding);
   }
 
   void EmitMiscDP2Source(MiscDP2SourceOp op,
                          Register rd, Register rn, Register rm,
                          OperandSize sz) {
     ASSERT((rd != SP) && (rn != SP) && (rm != SP));
+    ASSERT((sz == kDoubleWord) || (sz == kWord));

[regis, 2014/04/25 18:39:05]

Should kUnsignedWord be allowed as well? (here and at many other locations).

[zra, 2014/04/25 18:54:23]

Done.

     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     const Register crm = ConcreteRegister(rm);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
         (static_cast<int32_t>(crm) << kRmShift);
     Emit(encoding);
   }
 
   void EmitMiscDP3Source(MiscDP3SourceOp op,
                          Register rd, Register rn, Register rm, Register ra,
                          OperandSize sz) {
     ASSERT((rd != SP) && (rn != SP) && (rm != SP) && (ra != SP));
+    ASSERT((sz == kDoubleWord) || (sz == kWord));
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     const Register crm = ConcreteRegister(rm);
     const Register cra = ConcreteRegister(ra);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(cra) << kRaShift);
     Emit(encoding);
   }
 
+  void EmitCoditionalSelect(ConditionalSelectOp op,
+                            Register rd, Register rn, Register rm,
+                            Condition cond, OperandSize sz) {
+    ASSERT((rd != SP) && (rn != SP) && (rm != SP));
+    ASSERT((sz == kDoubleWord) || (sz == kWord));
+    const Register crd = ConcreteRegister(rd);
+    const Register crn = ConcreteRegister(rn);
+    const Register crm = ConcreteRegister(rm);
+    const int32_t size = (sz == kDoubleWord) ? B31 : 0;
+    const int32_t encoding =
+        op | size |
+        (static_cast<int32_t>(crd) << kRdShift) |
+        (static_cast<int32_t>(crn) << kRnShift) |
+        (static_cast<int32_t>(crm) << kRmShift) |
+        (static_cast<int32_t>(cond) << kSelCondShift);
+    Emit(encoding);
+  }
+
   void StoreIntoObjectFilter(Register object, Register value, Label* no_update);
 
   // Shorter filtering sequence that assumes that value is not a smi.
   void StoreIntoObjectFilterNoSmi(Register object,
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_