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Issue 2535703002: MIPS: Optimize load/store with large offset on MIPSr6 (Closed)
Patch Set: address comments Created 4 years ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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1933 emit(instr); 1933 emit(instr);
1934 } 1934 }
1935 1935
1936 1936
1937 // ------------Memory-instructions------------- 1937 // ------------Memory-instructions-------------
1938 1938
1939 // Helper for base-reg + offset, when offset is larger than int16. 1939 // Helper for base-reg + offset, when offset is larger than int16.
1940 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) { 1940 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {
1941 DCHECK(!src.rm().is(at)); 1941 DCHECK(!src.rm().is(at));
1942 DCHECK(is_int32(src.offset_)); 1942 DCHECK(is_int32(src.offset_));
1943 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask); 1943
1944 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset. 1944 if (kArchVariant == kMips64r6) {
1945 daddu(at, at, src.rm()); // Add base register. 1945 daui(at, src.rm(), hi);
ivica.bogosavljevic 2016/11/28 13:44:13 Does this compile? (hi is not defined anywhere)
Marija Antic 2016/11/29 12:17:03 Acknowledged.
1946 daddiu(at, at, src.offset_ & kImm16Mask);
1947 } else {
1948 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);
1949 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
1950 daddu(at, at, src.rm()); // Add base register.
1951 }
1946 } 1952 }
1947 1953
1948 // Helper for base-reg + upper part of offset, when offset is larger than int16. 1954 // Helper for base-reg + upper part of offset, when offset is larger than int16.
1949 // Loads higher part of the offset to AT register. 1955 // Loads higher part of the offset to AT register.
1950 // Returns lower part of the offset to be used as offset 1956 // Returns lower part of the offset to be used as offset
1951 // in Load/Store instructions 1957 // in Load/Store instructions
1952 int32_t Assembler::LoadRegPlusUpperOffsetPartToAt(const MemOperand& src) { 1958 int32_t Assembler::LoadRegPlusUpperOffsetPartToAt(const MemOperand& src) {
1953 DCHECK(!src.rm().is(at)); 1959 DCHECK(!src.rm().is(at));
1954 DCHECK(is_int32(src.offset_)); 1960 DCHECK(is_int32(src.offset_));
1955 int32_t hi = (src.offset_ >> kLuiShift) & kImm16Mask; 1961 int32_t hi = (src.offset_ >> kLuiShift) & kImm16Mask;
1956 // If the highest bit of the lower part of the offset is 1, this would make 1962 // If the highest bit of the lower part of the offset is 1, this would make
1957 // the offset in the load/store instruction negative. We need to compensate 1963 // the offset in the load/store instruction negative. We need to compensate
1958 // for this by adding 1 to the upper part of the offset. 1964 // for this by adding 1 to the upper part of the offset.
1959 if (src.offset_ & kNegOffset) { 1965 if (src.offset_ & kNegOffset) {
1960 if ((hi & kNegOffset) != ((hi + 1) & kNegOffset)) { 1966 if ((hi & kNegOffset) != ((hi + 1) & kNegOffset)) {
1961 LoadRegPlusOffsetToAt(src); 1967 LoadRegPlusOffsetToAt(src);
1962 return 0; 1968 return 0;
1963 } 1969 }
1964 1970
1965 hi += 1; 1971 hi += 1;
1966 } 1972 }
1967 1973
1968 lui(at, hi); 1974 if (kArchVariant == kMips64r6) {
1969 daddu(at, at, src.rm()); 1975 daui(at, src.rm(), hi);
1976 } else {
1977 lui(at, hi);
1978 daddu(at, at, src.rm());
1979 }
1970 return (src.offset_ & kImm16Mask); 1980 return (src.offset_ & kImm16Mask);
1971 } 1981 }
1972 1982
1973 void Assembler::lb(Register rd, const MemOperand& rs) { 1983 void Assembler::lb(Register rd, const MemOperand& rs) {
1974 if (is_int16(rs.offset_)) { 1984 if (is_int16(rs.offset_)) {
1975 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); 1985 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
1976 } else { // Offset > 16 bits, use multiple instructions to load. 1986 } else { // Offset > 16 bits, use multiple instructions to load.
1977 int32_t off16 = LoadRegPlusUpperOffsetPartToAt(rs); 1987 int32_t off16 = LoadRegPlusUpperOffsetPartToAt(rs);
1978 GenInstrImmediate(LB, at, rd, off16); 1988 GenInstrImmediate(LB, at, rd, off16);
1979 } 1989 }
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3505 3515
3506 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { 3516 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
3507 Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize); 3517 Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize);
3508 } 3518 }
3509 } 3519 }
3510 3520
3511 } // namespace internal 3521 } // namespace internal
3512 } // namespace v8 3522 } // namespace v8
3513 3523
3514 #endif // V8_TARGET_ARCH_MIPS64 3524 #endif // V8_TARGET_ARCH_MIPS64
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